在综合的时候timing完好，在PR的时候出现很大问题，求解释

无乐不作 · 发表于 2014-8-22 15:36:30

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下面是EDI中report_timing给出的时须报告，怎么读懂这个报告，报告中的other是什么意思？

Path 1: VIOLATED Data To Data Setup Check with Pin MI5/X151_X3/Q_reg/RN
Endpoint: MI5/X151_X3/Q_reg/S (v) checked with  leading edge of 'SPI_CLK'
Beginpoint: SPI_LE             (^) triggered by  leading edge of 'SPI_CLK'
Path Groups:  {in2reg}
Other End Arrival Time       0.959
- Data Check Setup             0.192
+ Phase Shift                0.000
= Required Time                0.767
- Arrival Time                9.567
= Slack Time                -8.800
   Clock Rise Edge                   0.000
   + Input Delay                      8.000
   + Drive Adjustment                0.279
   = Beginpoint Arrival Time          8.279
   Timing Path:
   +------------------------------------------------------------------------------------------------------+
   |             Instance             |    Arc    | Cell    |  Slew | Delay | Arrival | Required |
   |                                  |          |          |    |    |  Time | Time |
   |-------------------------------------+-------------+-------------+-------+-------+---------+----------|
   |                                  | SPI_LE ^ |          | 0.676 |    | 8.279 | -0.521 |
   | FE_OCP_RBC759_SPI_LE             | A ^ -> Z ^  | BUFFER_L | 0.085 | 0.174 | 8.453 | -0.346 |
   | u_CONTROL/FE_RC_1035_0             | D ^ -> Z ^  | OR4_J    | 0.216 | 0.241 | 8.694 | -0.105 |
   | u_CONTROL/FE_OCP_RBC966_X428_Z    | A ^ -> Z v  | INVERT_N | 0.235 | 0.153 | 8.847 | 0.048 |
   | MI26/MI117_X3/X162/M32             | A v -> Z v  | XNOR2_J    | 0.193 | 0.339 | 9.186 | 0.386 |
   | MI118/X1619_X3/U1                | A v -> Z ^  | INVERTBAL_H | 0.082 | 0.062 | 9.248 | 0.449 |
   | MI3/X1620_X3/U1                   | A1 ^ -> Z v | AOI21_C    | 0.303 | 0.167 | 9.416 | 0.616 |
   | MI5/X151_X3/FE_OCP_RBC1343_BUS4_19_ | A v -> Z ^  | INVERTBAL_H | 0.112 | 0.079 | 9.494 | 0.695 |
   | MI5/X151_X3/U3                   | A ^ -> Z v  | NOR2_E    | 0.108 | 0.072 | 9.567 | 0.767 |
   | MI5/X151_X3/Q_reg                | S v       | DFFSR_E    | 0.108 | 0.000 | 9.567 | 0.767 |
   +------------------------------------------------------------------------------------------------------+
   Clock Rise Edge                   0.000
   = Beginpoint Arrival Time          0.000
    Other End Path:
   +--------------------------------------------------------------------------------------------+
   |       Instance       |    Arc    | Cell    |  Slew | Delay | Arrival | Required |
   |                         |             |          |    |    |  Time | Time |
   |--------------------------+--------------+-------------+-------+-------+---------+----------|
   |                         | SPI_CLK ^ |          | 0.000 |    | 0.000 | 8.799 |
   | MI180/MI93_X3/X136/Q_reg | CLK ^ -> Q v | DFFR_K    | 0.129 | 0.362 | 0.362 | 9.162 |
   | MI26/MI117_X3/X162/M32 | B v -> Z ^ | XNOR2_J    | 0.222 | 0.360 | 0.723 | 9.522 |
   | MI118/X1619_X3/U1       | A ^ -> Z v | INVERTBAL_H | 0.080 | 0.060 | 0.782 | 9.582 |
   | MI3/X1620_X3/U1       | A1 v -> Z ^  | AOI21_C    | 0.359 | 0.176 | 0.958 | 9.758 |
   | MI5/X151_X3/Q_reg       | RN ^       | DFFSR_E    | 0.359 | 0.000 | 0.959 | 9.758 |
   +--------------------------------------------------------------------------------------------+
下面图片是相对应路径的原理图

schematic