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楼主 |
发表于 2014-7-31 10:43:48
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RTL:
module top(
TESTMODE,
pllbypass,
resetn,
testclk,
refclk,
test_si,
test_se,
test_so,
.....
);
pllclk u_pll(refclk, clk1x,clk2x,clk3x, ..... ); //手动生成的,只包含端口定义, PLL.db
M1 u1(.inputclk(clk1x), ...... );
M2 u2(.inputclk(clk2x), ...... );
M3 u3(.inputclk(clk3x), ...... );
...
endmodule |
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