Development of Self-Calibrating A-D Converters

fhchen2002

Spring 2014 issue of IEEE Solid-State Circuits Magazine
Author: H.-S. Lee
Title: Development of Self-Calibrating A-D Converters

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Development of Self-Calibrating A-D Conveters

Introduction
The data converters – analog-to-digital and digital-to-analog converters (ADC’s
and DAC’s respectively) – provide an important interface function between
analog and digital circuits in most electronic systems. As MOS integrated circuit technologies began
to replace bipolar technologies in the 1960s and 1970s, it became realistic to integrate both complicated digital and
high performance analog circuits on a single silicon die. Therefore, there emerged a strong need for MOS data converters.
The most popular data converter architecture for bipolar integrated circuits was an R-2R ladder and its variants.
However, the lack of precision resistors and low transconductance in MOS transistors made the R-2R ladder difficult
to provide comparable accuracy in MOS technologies.

For analog circuit applications, the benefits of MOS technology included the availability of high quality capacitors,
excellent switching characteristics, and the zero gate current. The weakness were the aforementioned resistor accuracy,
low transconductance, and lower power supply voltages.  Radically different circuit architectures that exploited the
benefits while avoiding the drawbacks of MOS technology were needed. The switched-capacitor filters were a
great example of such architecture [1]. In the similar line of thoughts, James McCreary along with Profs. Paul Gray and
David Hodges, came up with an innovative ADC architecture using switched capacitors [2]. Rather than employing a separate
sample-and-hold amplifier (SHA), which was a common practice in successive approximation ADC’s, the input was
sampled directly on the binary weighted capacitor array.  Not only this eliminated the need for a separate SHA with
associated power, noise, and area, it also removed the linearity degradation due to the nonlinear parasitic capacitance
at the input of the comparator. The result was 10-bit accuracy primarily limited by the capacitor ratio matching. This
technique referred to as charge-redistribution ADC would become the most dominant successive approximation ADC
architecture for the next 4 decades.

jamesccp

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shuming221

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amigo.change

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fhchen2002

是从 IEEE Solid-State Circuits Magazine 节录下来的

gujm

感謝楼主的分享

qmax

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liuzhieetop

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thwang0

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liuminghang1993

thx~~