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发表于 2022-3-29 12:08:50
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显示全部楼层
// VerilogA for osc, veriloga
`include "constants.vams"
`include "disciplines.vams"
module i_pulse(in,out);
input in ;
output out ;
electrical in , out ;
parameter real period = 1n from (0:inf) ;
parameter real ref = 40u from (0:inf) ;//
integer x ;
real y ;
real n=0;
real N=10;
analog begin
if(V(in) < ref) begin
x = -1; end
else begin
x = 1 ;
end
@(cross(x,1)) begin
n=n+1;
if(n>N) begin
N=N+1
n=0;
if(y==0) y= -80u;
else if(y==-80u) y=0;
end
end
I(out) <+ transition(y, 0, 1p, 1p) ;
end
endmodule
你可以参考一下
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