大家帮我看看这个100进制计数器VHDL的设计有没有问题

656141806

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt100 is
   port(clk:in std_logic;           q ut std_logic_vector(7 downto 0);
           c: out std_logic);
end cnt100;
architecture one of cnt100 is
signal qa:std_logic_vector(3 downto 0);
signal qb:std_logic_vector(3 downto 0);
signal cin:std_logic;
begin
   q(3 downto 0)<=qa;

q(7 downto 4)<=qb;
   process(clk)

begin

   if clk'event and clk='1' then

   if qa=9 then qa<="0000";cin<='1';

else qa<=qa+1;cin<='0';

end if;

end if;

end process;

process(clk,cin)

begin

     if clk'event and clk='1' then

     if (qb=9 and qa=9) then qb<="0000";c<='1';

  else c<='0';

  end if;

  if cin='1' then qb<=qb+1;

  end if;

end if;

end process;
end one;

shiyinjita

仿真一下就可以的

Arvinliu

路过，不懂

轩爸

通过波形仿真，分分钟就可以得出结果