关于verilog的两道题，求大神解答

mikexavi · 发表于 2013-11-2 21:00:36

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1.使用verilog工具实现一个16位计数器，要求：分别使用RTL级和门级描述方式（门级写成单元写法即可，不要求完整过程）

2.使用verilog实现16位数据串转并输入，并寄存，要求RTL级描述。（接口自己设计）

本人初学者，这两道题一知半解的，请大家赐教，先谢谢了

yinqingyu · 发表于 2013-11-3 20:02:00

本帖最后由 yinqingyu 于 2013-11-3 20:21 编辑

module counter(clk,rst_n,key_n,led_7);
  input clk,rst_n,key_n;
  output reg [13:0] led_7;
  reg key_r;
  reg [9:0] cnt;
  reg [7:0] count;

always @ (posedge clk or negedge rst_n)
if(!rst_n)
cnt <=  10'b0;
else
begin if(key_n)
         begin cnt <= 10'b0; key_r <=1'b1; end
   else begin
                  if(cnt == 10'd200) begin cnt <= 10'b0; key_r <= 1'b0;end
                  else                      cnt <= cnt + 1'b1;
                  end
end

always @(negedge key_r or negedge rst_n)
begin
if(!rst_n)
count = 8'b0;
else
count = count + 1'b1;
end

always @(count)
begin

case (count[3:0])
4'b0000: led_7[6:0] = 7'b1000000; //0
4'b0001: led_7[6:0] = 7'b1111001; //1
4'b0010: led_7[6:0] = 7'b0100100; //2
4'b0011: led_7[6:0] = 7'b0110000; //3
4'b0100: led_7[6:0] = 7'b0011001; //4
4'b0101: led_7[6:0] = 7'b0010010; //5
4'b0110: led_7[6:0] = 7'b0000010; //6
4'b0111: led_7[6:0] = 7'b1111000; //7
4'b1000: led_7[6:0] = 7'b0000000; //8
4'b1001: led_7[6:0] = 7'b0010000; //9
4'b1010: led_7[6:0] = 7'b0001000; //a
4'b1011: led_7[6:0] = 7'b0000011; //b
4'b1100: led_7[6:0] = 7'b1000110; //c
4'b1101: led_7[6:0] = 7'b0100001; //d
4'b1110: led_7[6:0] = 7'b0000100; //e
4'b1111: led_7[6:0] = 7'b0001110; //f
default: led_7[6:0] = 7'b1111110; //x
endcase

case (count[7:4])
4'b0000: led_7[13:7] = 7'b1000000; //0
4'b0001: led_7[13:7] = 7'b1111001; //1
4'b0010: led_7[13:7] = 7'b0100100; //2
4'b0011: led_7[13:7] = 7'b0110000; //3
4'b0100: led_7[13:7] = 7'b0011001; //4
4'b0101: led_7[13:7] = 7'b0010010; //5
4'b0110: led_7[13:7] = 7'b0000010; //6
4'b0111: led_7[13:7] = 7'b1111000; //7
4'b1000: led_7[13:7] = 7'b0000000; //8
4'b1001: led_7[13:7] = 7'b0010000; //9
4'b1010: led_7[13:7] = 7'b0001000; //a
4'b1011: led_7[13:7] = 7'b0000011; //b
4'b1100: led_7[13:7] = 7'b1000110; //c
4'b1101: led_7[13:7] = 7'b0100001; //d
4'b1110: led_7[13:7] = 7'b0000100; //e
4'b1111: led_7[13:7] = 7'b0001110; //f
default: led_7[13:7] = 7'b1111110; //x
endcase
end
endmodule
这是我写的16进制的两位计数器，并且用数码管显示的程序，中间加了去抖，如果不用的话，可自行删除，希望对你有用。
module c_to_b_8(clk,rst_n,c,b);
input clk,rst_n;
input c;
output reg [7:] b;
reg [2:0] state,nextstate;

always @(posedge clk or negedge rst_n)
if(!rst_n) state <= 0;
else state <= neststate;

always @(state)
case (state)
   3'd0: begin b[0] = c; neststate <= 3'd1;
   3'd1: begin b[1] = c; neststate <= 3'd2;
   3'd2: begin b[2] = c; neststate <= 3'd3;
   3'd3: begin b[3] = c; neststate <= 3'd4;
   3'd4: begin b[4] = c; neststate <= 3'd5;
   3'd5: begin b[5] = c; neststate <= 3'd6;
   3'd6: begin b[6] = c; neststate <= 3'd7;
   3'd7: begin b[7] = c; neststate <= 3'd8;

endmodule
这是8位串转换并

mikexavi · 发表于 2013-11-3 20:53:57

回复 2# yinqingyu

学习了，真心感谢

加油99 · 发表于 2013-11-6 15:13:12

本帖最后由加油99 于 2013-11-6 15:22 编辑

门级描述方式的计数器，我写个4位的。16位太长，以此类推就行。
reg [3:0]cnt;
always @(posedge clk)
begin
cnt[0] <= ~cnt[0];
cnt[1] <= cnt[1]&~cnt[0]
               | ~cnt[1]&cnt[0];
cnt[2] <= cnt[2]&~cnt[1]
               | cnt[2]&~cnt[0]
               | ~cnt[2]&cnt[1]&cnt[0] ;
cnt[3] <= cnt[3]&~cnt[2]
               | cnt[3]&~cnt[1]
               | cnt[3]&~cnt[0]
               | ~cnt[3]&cnt[2]&cnt[1]&cnt[0] ;
end
这个always等价于：
always @(posedge clk)
cnt <= cnt + 1'b1;