phd thesis (high speed SAR ADC in detail)

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dudiaoke

phd thesis (high speed SAR ADC in detail)

dudiaoke

HIGH SPEED SUCCESSIVE APPROXIMATION ADC AND ITS APPLICATIONS
by
Masoud Ensafdaran

Data converters are required in many applications such as serial link, wireless communication
and clock generation circuits. For example, analog to digital converters (ADCs) are usually
time-interleaved to implement very high speed ADCs in serial link and ultra wide-band
(UWB) receivers. Phase to digital conversion is also a critical building block of digital
phase locked loops (DPLLs). With recent advancements in speed and power consumption,
successive approximation ADCs (SAR ADCs) have achieved significant attention. The focus
of this dissertation is on the design of a high speed and low power SAR ADC. The main
target application of our ADC is time-interleaved ADCs and DPLLs.
Several new techniques are proposed to realize a single-stage 10b 250MS/s SAR ADC. A
double capacitor-array digital to analog converter (DAC) with top plate sampling enables
the use of simple switch circuitry with faster settling time while improving power efficiency.
The ADC also employs a two-speed variable clock generator to exploit the reduced DAC
settling time requirements. A semi-dynamic comparator modified for low voltage design is
used to achieve fast decision and reset times. A multiple latch based SAR logic decreases

dudiaoke

phd thesis (high speed SAR ADC in detail

acer1128

   

phd thesis (high speed SAR ADC in detail)
dudiaoke 发表于 2013-10-20 13:16

                               
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dudiaoke

Data converters are required in many applications such as serial link, wireless communication
and clock generation circuits. For example, analog to digital converters (ADCs) are usually
time-interleaved to implement very high speed ADCs in serial link and ultra wide-band
(UWB) receivers. Phase to digital conversion is also a critical building block of digital
phase locked loops (DPLLs). With recent advancements in speed and power consumption,
successive approximation ADCs (SAR ADCs) have achieved significant attention. The focus
of this dissertation is on the design of a high speed and low power SAR ADC. The main
target application of our ADC is time-interleaved ADCs and DPLLs.
Several new techniques are proposed to realize a single-stage 10b 250MS/s SAR ADC. A
double capacitor-array digital to analog converter (DAC) with top plate sampling enables
the use of simple switch circuitry with faster settling time while improving power efficiency.
The ADC also employs a two-speed variable clock generator to exploit the reduced DAC
settling time requirements. A semi-dynamic comparator modified for low voltage design is
used to achieve fast decision and reset times. A multiple latch based SAR logic decreases
vi

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