毕业生的疑惑

501940245

我今年刚毕业，想去英盛德培训，不知道做数字后端好，还是数字前端好呢？ 前辈们给些意见吧！

love80238023

个人意见，硕士的话后端挺好

729050850

英盛德芯片设计学院（Nottingham-Sondrel School of VLSI Design）课程设置有：

  课程概况
学时   2013年6月至2013年9月   
招生对象  电子工程、微电子、芯片设计、计算机、电信、物理、机械等专业本科生、研究生   
主要课程模块   基础课程、系统设计和验证、功能验证、物理设计和测试设计   
师资力量   教授、项目经理、资深工程师   
课时安排   正规课程、自我陈述、实践操作是每日必修内容，一周五天上课时间;
实验室将一周七天对学生开放，供学生完成日常作业或练习项目开发


  
课程信息 Primer

Foundation

. Applied Digital System Design
.Digital Design Fundamentals-I – Number Systems, Combinational Digital Systems
.Digital Design Fundamentals-II – Synchronous, Sequential Logic
.Introduction to Programmable Logic
.Data-path elements – Arithmetic
.Structures, Floating point
Numbers
.Synchronous Finite State Machines and Memories
.Low Power Design Methodology
.Clock Domain Crossing Techniques
.Design For Test
.Introduction to ASICs
.Introduction to Programmable Platforms
  
Verilog HDL

. Hardware Modelling Overview, Verilog language concepts
. Modules and Ports, Demo for usage of ISE for HDL usage
. Introduction to Test benches
. Operators, Dataflow
. Procedural Statements
. Controlled Operation Statements
. Tasks and Functions
. Finite State Machines
. Advance Language Concepts
. Advanced Verilog Test benches
. Synchronous design techniques
. Verilog Coding For Synthesis
. Verilog Assertions
. Simulation vs. synthesis
. Design for verification
. Design for Test (DFT)
. Comparison between VHDL and Verilog
Microprocessor: CPU Architecture

. Instruction set
. ARM and Thumb mode
. LPC 2378 Processor Architecture
. GPIO - LPC 2378 (Switch, LED)
. ARM code Optimization Techniques
. Interrupt, Exception, IRQ, FIQ
. System Peripherals, ADC, Timer/Counter,
. UART
. Protocols SPI, I2C
   
System Design & Validation

Introduction to IPs

. Introduction to IP as basics of SoC Building block Protocols SPI, 12C
. IP classifications i.e. IO, Interconnect, Memory, DFT, CPU, GPU
. IO Pad, I2C, PCIE, USB, SATA, Fiber Channel, Thunderbolt etc.
. Functional descriptions of each
. Functional Specs
. Standard Organizations, IP Compliance & Inter-Operability
. ESD    Internal IPs

. Memory Macro, MemBist
. PLL, DLL
. JTAG controller
. CPU & GPU
   IP Integration &Validation

. Protocols SPI, 12C
. IPs and VIPs
. Validation Approaches
. System Level Performance, Compliance Analysis
. Low Power Design Techniques
   

  

Functional Verification I

. Introduction to Verification, Verification Cycle
. Different types of Test Benches
. Verification Tools, Stimulus and Response
. Introduction to BFMs    . Verification environment and its components
. Introduction to Verification Plan
. Coverage Driven Verification
. Different types of Code Coverage
   
Functional Verification II(System Verilog/UVM)

Introduction to System Verilog

. Introduction to SV
. Enhancement to System Verilog
. Array Structures & Unions
. Interface and Mod ports
. OOP's Concept of System Verilog
. Inheritance
. Virtual methods and class
System Verilog Assertions

. Introduction to Assertion
. Overview of properties and assertion
.SVA Properties and operators
. SVA Sequences and operators
. Checkers
. Assertions in design, formal verification and Assertions for Coverage
  
  System Verilog Verification Constructs

. Constrained Randomization Techniques
. System Verilog Event Ordering
. Clocking block and Program block
. Functional Coverage
. Class Based verification environment using SV constructs
Introduction to UVM

. Introduction to UVM
. Getting Started with UVM
. Monitors and Reporting
. Checkers and Score boards
. Functional Coverage
.Random Stimulus Generation
.Configuring the Testbench
.Agent Architecture
.Sequences More on Sequences   


  

Physical Design & Design for Test

Design for Test

. Analyze ATPG messaging
. Perform advanced test methodologies
. Troubleshoot areas of low test coverage
.Troubleshoot DRC violations and simulation mismatches
.Use TessentTestKompress to create compact pattern sets
Physical Design Course

. Introduction & algorithm paradigm
. Partitioning & Floor planning
. Placement
. Clock tree synthesis and Routing
. Signal/power integrity: noise & modelling & optimization, IR drop Design closure: Timing, PV, FV, POWER
Design for manufacture ability & reliability   

课程内容全面而且高端，连续3个月的全日制培训，比国内其他的IC培训机构要好多少倍，不知道需要多少费用？

501940245

要2万，还是在宁波培训

lymrlym

做后端吧。后端相对竞争少些。