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AMD超威半导体上海研发中心ASIC DesignEngineer - Display
招聘2016届应届毕业生,请相关专业有兴趣的同学将个人简历以附件的形式发送至邮箱:Nina.Zhang@amd.com
[url=mailto:以及Jina.Wang3@amd.com]以及Jina.Wang3@amd.com[/url]
来信请注明:姓名-专业-学校-毕业时间-申请职位。
Responsibilities:
- Responsible for display IP development and maintenance
- Responsible for IP level synthesis/formal check
- Work with verification engineer on IP level validation
- Work with front-end integration team and physical design team on timingclosure
- Communication with driver team to build driver
Requirements:
- Bachelor with 5+ yeas and Master with 3+ in Electrical orComputer Engineering.
- Strong RTL coding and familiar with front-end design flow
- Experience on synthesis, timing analysis and formal verification.
- Experience of display specific-interconnection protocols (DisplayPort, LVDS,VGA,HDCP, DVI, HDMI etc) is a plus.
- Design for verification (assertion based design strategies, code coverage,functional
coverage, test plan etc.)
- Good communication skills and fluent English.
- Strong responsibilities and team spirit.
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