贴出verilog文件以及综合script，请大侠帮我看看哪里出错

ttxs2009

以下是我从别人那里得到的verilog文件，使用system verilog的语法来写的。

顶层模块叫做TopDigital。底层模块叫做UpdateUnit, ComputeUnit, PulseGen 以及 SystemController。

底层模块都可以各自成功综合，而且用encounter也能画出版图。

顶层模块虽然综合的过程中没有error，但是感觉底层模块没有加进来，是block box，而且report area 是0.000和undefined。这样的话，用SoC encounter 来看的话，报告就是

Found empty module (UpdateUnit).Found empty module (SystemController).Found empty module (PulseGen).Found empty module (ComputeUnit).
#####################################################################

`timescale 1ns/1ps

`include "UpdateUnit.v"

`include "ComputeUnit.v"

`include "PulseGen.v"

`include "SystemController.v"

module
TopDigital(
CLK,
nRST,
PCLK,
PnRST,
WENEXTSPIKES,
EXTSPIKES,
//Parameters
VLEAK,
VREST,
VTHRES,
KEXT,
KSYN,
COMPUTETYPES,
READPULSECNT,
TIMESCALE,
WENCHANGES,
ZEROCHANGE,
PRESYNCHANGES,
POSTSYNCHANGES,
WENPULSECNTS,
PULSECNTS,
OUTSPIKES,

//Interface with Analog Part
SYNWEIGHTS,
CONNECTIONS,
ADCOUT_XB,
CS_XB,
WEN_XB,
COLEN_XB,
ADDR_XB,
PULSES_XB,
PULSESIGNS_XB

);
parameter
pNUM_COMPUTES= 256;
parameter  pADDR_WIDTH= $clog2( pNUM_COMPUTES );
parameter
pPULSE_RESOL= 10;
parameter pTIMER_RESOL= 10;
parameter pSCALE_RESOL= 3;

parameter
pSYNAPSE_RESOL= 3;

parameter pNUM_STDPENTRIES= 8;

parameter
pNUM_PWMENTRIES= 2 ** pSYNAPSE_RESOL;

parameter
pMEMB_RESOL= 16;

parameter
pPARAM_RESOL= 5;

parameter
pADC_RESOL= pADDR_WIDTH + pSYNAPSE_RESOL;

input logic CLK;
input logic nRST;
input logic PCLK;
input logic PnRST;
input logic WENEXTSPIKES;
input logic [pNUM_COMPUTES-1:0] EXTSPIKES;
input logic [pMEMB_RESOL-1:0] VLEAK;

input logic [pMEMB_RESOL-1:0] VREST;
input logic [pMEMB_RESOL-1:0] VTHRES;
input logic [pPARAM_RESOL-1:0] KEXT;
input logic [pPARAM_RESOL-1:0] KSYN;
input logic COMPUTETYPES[0:pNUM_COMPUTES-1];
input logic [pPULSE_RESOL-1:0] READPULSECNT;
input logic [pSCALE_RESOL-1:0] TIMESCALE;
input logic WENCHANGES;
input logic [pSYNAPSE_RESOL:0] ZEROCHANGE;
input logic [pSYNAPSE_RESOL:0] PRESYNCHANGES [0:pNUM_STDPENTRIES-1];
input logic [pSYNAPSE_RESOL:0] POSTSYNCHANGES[0:pNUM_STDPENTRIES-1];

input logic WENPULSECNTS;
input logic [pPULSE_RESOL-1:0] PULSECNTS[0:pNUM_PWMENTRIES-1];
output logic [pNUM_COMPUTES-1:0] OUTSPIKES;
//

//
Interface with Analog Part

//

input logic [pSYNAPSE_RESOL-1:0]SYNWEIGHTS[0:pNUM_COMPUTES-1];
input logic [pNUM_COMPUTES-1:0] CONNECTIONS;
input logic [pADC_RESOL-1:0] ADCOUT_XB;
output logic CS_XB;
output logic WEN_XB;
output logic COLEN_XB;
output logic [pADDR_WIDTH-1:0] ADDR_XB;
output logic PULSESIGNS_XB[0:pNUM_COMPUTES-1];
output logic PULSES_XB[0:pNUM_COMPUTES-1];

logic DONE_NU_;

logic DONE_LU_;

logic START_NU_;

logic START_LU_;

logic START_PGLU_;

logic WRITE_PGLU_;

logic COLUMN_PGLU_;

logic [pADDR_WIDTH-1:0] ADDR_PGLU_;

logic PULSESIGNS_PGLU_[0:pNUM_COMPUTES-1];

logic [pPULSE_RESOL-1:0] PULSEWIDTHS_PGLU_[0:pNUM_COMPUTES-1];

logic START_PGNU_;

logic WRITE_PGNU_;

logic CONUMN_PGNU_;

logic [pADDR_WIDTH-1:0] ADDR_PGNU_;

logic PULSESIGNS_PGNU_[0:pNUM_COMPUTES-1];

logic [pPULSE_RESOL-1:0] PULSEWIDTHS_PGNU_[0:pNUM_COMPUTES-1];

logic START_PG_;

logic WRITE_PG_;

logic COLUMN_PG_;

logic [pADDR_WIDTH-1:0] ADDR_PG_;

logic PULSESIGNS_PG_[0:pNUM_COMPUTES-1];

logic [pPULSE_RESOL-1:0] PULSEWIDTHS_PG_[0:pNUM_COMPUTES-1];

logic DONE_PG_;

logic [pADDR_WIDTH:0]NFIREPRE_[0:pNUM_COMPUTES-1];

logic[pTIMER_RESOL-1:0]GLOBALTIME_;

SystemController

#(

pTIMER_RESOL,
//
= 10,

pPULSE_RESOL,
//
= 10,

pNUM_COMPUTES
//
=256

)

iSystemController(

.CLK
(CLK),

.nRST
(nRST),

.DONE_NU
(DONE_NU_),

.DONE_LU
(DONE_LU_),

.START_NU
(START_NU_),

.START_LU
(START_LU_),

.WENEXTSPIKES
(WENEXTSPIKES),

.PREVSPIKES
(OUTSPIKES),

.GLOBALTIME
(GLOBALTIME_),

//

//
Pulse Generator Interface

//

.START_PGNU
(START_PGNU_),

.WRITE_PGNU
(WRITE_PGNU_),

.COLUMN_PGNU
(COLUMN_PGNU_),

.ADDR_PGNU
(ADDR_PGNU_),

.PULSESIGNS_PGNU
(PULSESIGNS_PGNU_),

.PULSEWIDTHS_PGNU
(PULSEWIDTHS_PGNU_),

.START_PGLU
(START_PGLU_),

.WRITE_PGLU
(WRITE_PGLU_),

.COLUMN_PGLU
(COLUMN_PGLU_),

.ADDR_PGLU
(ADDR_PGLU_),

.PULSESIGNS_PGLU
(PULSESIGNS_PGLU_),

.PULSEWIDTHS_PGLU
(PULSEWIDTHS_PGLU_),

.START_PG
(START_PG_),

.WRITE_PG
(WRITE_PG_),

.COLUMN_PG
(COLUMN_PG_),

.ADDR_PG
(ADDR_PG_),

.PULSESIGNS_PG
(PULSESIGNS_PG_),

.PULSEWIDTHS_PG
(PULSEWIDTHS_PG_)

);

UpdateUnit

#(

pTIMER_RESOL,
//
= 10,

pSCALE_RESOL,
//
= 3,

pNUM_STDPENTRIES,
//
=8,

pPULSE_RESOL,
//
= 10,

pSYNAPSE_RESOL,
//
= 3,

pNUM_COMPUTES
//
= 256

)

iUpdateUnit(

.CLK
(CLK),

.nRST
(nRST),

.START
(START_LU_),

.FIRSTCOMPUTENUM
(8'd0),

.LASTCOMPUTENUM
(8'd255),

.CURSPIKES
(OUTSPIKES),

.GLOBALTIME
(GLOBALTIME_),

.TIMESCALE
(TIMESCALE),

.WENCHANGES
(WENCHANGES),

.ZEROCHANGE
(ZEROCHANGE),

.PRESYNCHANGES
(PRESYNCHANGES),

.POSTSYNCHANGES
(POSTSYNCHANGES),

.WENPULSECNTS
(WENPULSECNTS),

.PULSECNTS
(PULSECNTS),

//
XBAR

.SYNWEIGHTS
(SYNWEIGHTS),

.CONNECTIONS
(CONNECTIONS),

//
Compute Unit

.NFIREPRE
(NFIREPRE_),

//
Pulse Generator

.DONE_PG
(DONE_PG_),

.START_PG
(START_PGLU_),

.WRITE_PG
(WRITE_PGLU_),

.COLUMN_PG
(COLUMN_PGLU_),

.ADDR_PG
(ADDR_PGLU_),

.PULSESIGNS_PG
(PULSESIGNS_PGLU_),

.PULSEWIDTHS_PG
(PULSEWIDTHS_PGLU_),

.DONE
(DONE_LU_)

);

ComputeUnit

#(

pMEMB_RESOL,
//
= 16,

pPARAM_RESOL,
//
=5,

pSYNAPSE_RESOL,
//
=3,

pPULSE_RESOL,
//
= 10,

pNUM_COMPUTES
//
=256

)

iComputeUnit(

.CLK
(CLK),

.nRST
(nRST),

.START
(START_NU_),

//Parameters

.VLEAK
(VLEAK),

.VREST
(VREST),

.VTHRES
(VTHRES),

.KEXT
(KEXT),

.KSYN
(KSYN),

.COMPUTETYPES
(COMPUTETYPES),

.READPULSECNT
(READPULSECNT),

.FIRSTCOMPUTENUM
(8'd0),

.LASTCOMPUTENUM
(8'd255),

.NFIREPRE
(NFIREPRE_),

//
External Spike I/O

.WENEXTSPIKES
(WENEXTSPIKES),

.EXTSPIKES
(EXTSPIKES),

//
XBAR

.ADCOUT_XB
(ADCOUT_XB),

//
Pulse Generator

.DONE_PG
(DONE_PG_),

.START_PG
(START_PGNU_),

.WRITE_PG
(WRITE_PGNU_),

.COLUMN_PG
(COLUMN_PGNU_),

.ADDR_PG
(ADDR_PGNU_),

.PULSESIGNS_PG
(PULSESIGNS_PGNU_),

.PULSEWIDTHS_PG
(PULSEWIDTHS_PGNU_),

.OUTSPIKES
(OUTSPIKES),

.DONE
(DONE_NU_)

);

PulseGen

#(

pNUM_COMPUTES,
//
=256,

pPULSE_RESOL
//
=10

)

iPulseGen

(

.PCLK
(PCLK),

.PnRST
(PnRST),

.START
(START_PG_),

.WRITE
(WRITE_PG_),

.COLUMN
(COLUMN_PG_),

.ADDR
(ADDR_PG_),

.PULSESIGNS
(PULSESIGNS_PG_),

.PULSEWIDTHS
(PULSEWIDTHS_PG_),

.CS_XB
(CS_XB),

.WEN_XB
(WEN_XB),

.COLEN_XB
(COLEN_XB),

.ADDR_XB
(ADDR_XB),

.PULSES_XB
(PULSES_XB),

.PULSESIGNS_XB
(PULSESIGNS_XB),

.DONE
(DONE_PG_)

);

endmodule

我感觉我的问题是出在综合，以下就是我综合用的脚本。 大侠请帮我看看，我是哪里犯错了。

set bus_naming_style {%s[%d]}

set hdlin_ff_always_sync_set_reset "true"

set hdlin_latch_always_async_set_reset "true"

set compile_preserve_sync_resets "true"

set change_names_dont_change_bus_members "true"

read_file -format sverilog {../rtl/Top.v}

current_design TopDigital

link

list_design

uniquify

check_design -multiple_designs

set_flatten -design [find design "*"] false

set_structure -design [find design "*"] false

set_max_area 0

set_max_leakage_power 0

set_max_dynamic_power 0

create_clock [get_ports CLK] -period 1000

set_dont_touch_network [find
port
"CLK"]

set_dont_touch_network [find port "nRST"]

set_fix_multiple_port_nets -all -buffer_constants

set_structure true -boolean true -timing false-boolean_effort high -design [find design *]

compile -map_effort high

write -f ddc -hier -out
./gate/TopDigital.ddc

write_sdc
./gate/TopDigital.sdc

write_sdf
./gate/TopDigital.sdf

write_parasitics -output
./gate/TopDigital.spf

write -f verilog -hier -out ./gate/TopDigital.gate.v

report_timing >
./result/TopDigital.timing

report_power >
./result/TopDigital.power

report_area >
./result/TopDigital.area

report -reference -area >
./result/TopDigital.ref

kk2009

这么小的design，做syn的时候可以top down 做综合。