physical design manager(Shanghai)

Mrbear

Physical design Leader 这个是带团队的，需要技术和个人魅力都结合的职位
1. lead soc design team;  
2. be able to interface &communicate with internal colleague and external customer;   
3. be able to provide design guidance and instruction to engineers;   
4. be able to hands-on work on Top level/block level physical design independently  
   
JR:  
1. minimum of 5 yrs of working experience;   
2. master degree of EE or related field is preferred;   
3. team leader or functional leader experience is preferred;  
4. familiar with either Synopsys or Cadence design flow and EDA tools;   
5. fluent in both Chinese and English  
   
下面的职位要求，有其中之一最好没有也不强调：  
1. Responsible for all aspects of physical design and implementation of integrated circuits and other ASIC.   
2. Responsibilities include: Participating in the efforts in establishing CAD and physical design methodologies;  
3. Focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology);  
4, Chip floor plan; Power/clock distribution;   
5. Chip assembly and P&R; Timing closure;   
6. Power and noise analysis;   
7. Back-end verification across multiple projects;   
   
Requirements:   
1. BSEE 5+years,MSEE 3+years experience in large VLSI physical design implementation;   
2. Successful track record of delivering products to production is a must;   
3. Understanding of custom Macro blocks such as RAMs, PLLs, high-speed IO drivers;   
4. Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues;   
5. Working knowledge of deep sub-micron routing issues as they relate to power and timing;   
6. Circuit level comprehension of time critical paths. Spice experience a plus;   
7. Should be a power user of Apollo/Astro for routing, PhysOpt (Physical Compiler) for placement, PrimeTime for Timing Verification, dc_shell etc.  
   
PR Engneer  
   
Responsibilities:   
1. Layout database creation : layout library and Milkyway database creation;   
2. Initial floorplan : Initial chip or subchip level floorplan;  
3. Place & Route: Perform cells placement; Perform global route and detail route;  
4.  DRC/LVS corrections; Layout script creation: Create script to perform layout modification;   
5. Create Apollo scheme file to maintain and update Apollo database;   
6. Layout modification: Follow signal integration report to perform necessary modification;   
7. Requirements: Bachelor Degree or higher in EE major;  
8. 0-3 years P&R working experience;   
9. Knowledge about Solaris/Unix/Linux operating system; Good command of English in both written and oral format.   

DFT Engineer

1. Responsibilities: Synthesis: Use DC (Design Compiler), ACS (Advanced Chip Synthesis), and PC (Physical Compiler) for chip synthesis either from RTL code or Gate level netlist;  
2. Static Timing analysis and Formal verification: Perform timing analysis and timing optimization;   
3. Run formal verification after each ECO and timing optimization;   
4. DFT design: Scan chain insertion; JTAG/Boundary scan insertion; NAND tree insertion;  
5. Memory BIST insertion; Logic BIST insertion;  
6. Test pattern generation and simulation: ATPG test vector generation and pattern simulation;  
7. Fault grading test vector generation;   
8. Memory BIST simulation; JTAG/NAND tree simulation;   
9. Test vectorl format conversion and provide all test related patterns to test and product engineers;   
10. Requirements: BS, MS preferred; 0-3 years working experience on chip integration;  
11. Strong Logic design and Semiconductor device physic background; Good English in both written and spoken.

有兴趣的朋友可以联系我aaron_bear@163.com，谢谢。

Mrbear

有兴趣的朋友可以邮箱联系我，了解详细情况。

Mrbear

目前职业依然有效，有兴趣的朋友抓紧了。