Verilog writer has added 1 nets to module halfband3_DW02_mult_17 using SYNOPSYS_UNCONNECTED_ as prefix. Please use the change_names command to make th e correct changes before invoking the verilog writer.(VO-11)
Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4)
Warning: Verilog writer has added 1 nets to module halfband_DW02_mult_3 using SY NOPSYS_UNCONNECTED_ as prefix. Please use the change_names command to make the correct changes before invoking the verilog writer. (VO-11)
Warning: Verilog writer has added 1 nets to module halfband_DW02_mult_1 using SY NOPSYS_UNCONNECTED_ as prefix. Please use the change_names command to make the correct changes before invoking the verilog writer. (VO-11)
Warning: Verilog writer has added 27 nets to module halfband using SYNOPSYS_UNCO NNECTED_ as prefix. Please use the change_names command to make the correct cha nges before invoking the verilog writer. (VO-11)
然后我在做ICC时就出现了很多类似下面的错误，还请赐教是怎么回事啊？
Error: Port 'halfband_out_f[2]' cannot inherit its location from the pin 'hb3/out_r_reg[18]/Q', because the cell 'hb3/out_r_reg[18]' is neither a pad-cell nor a macro-cell. Please check the library. (PSYN-117)
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发表于 2013-6-6 21:48:55
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发表于 2013-6-7 07:42:26
