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发表于 2013-3-6 22:39:47
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看看这个方案可行吗?
因为时钟可能采样不到输入信号的高电平,所以用脉冲上沿触发输出脉冲的上沿,然后用时钟计数,完成delay时间后,将输出脉冲复位到0。
要注意的是,输入脉冲上沿是否和clk是异步关系。
以下是参考的code
input clk, pulse_in, reset;
output pulse_out;
reg clear ;
reg pulse_in_rise_sync_q, pulse_in_rise_sync_qq;
always @(posedge pulse_in or posedge clear) begin
if (clear) pulse_in_rise <= 1'b0;
else pulse_in_rist <= 1'b1;
end
always @(posedge clk or posedge reset) begin
if (reset) begin
pulse_in_rise_q <= 1'b0;
pulse_in_rise_qq <= 1'b0;
end
else begin
pulse_in_rise_q <= pulse_in_rise;
pulse_in_rise_qq <= pulse_in_rise_q;
end
end
always @(posedge clk or negedge pulse_in_rise_qq) begin
if (~pulse_in_rise_qq)
cnt <= 0;
else
cnt <= cnt +1 ;
end
always @(posedge clk or posedge reset) begin
if (reset) clear <= 1'b0;
else clear <= cnt == expect_numer
end |
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