|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
现在在做输出偏移约束感觉比较奇怪的问题就是在约束一组八位数据的输出时有几位的结果差异很大具体如下：
- Paths for end point dout<2> (W20.PAD), 1 path
- --------------------------------------------------------------------------------
- Slack (slowest paths): -3.279ns (requirement - (clock arrival + clock path + data path + uncertainty))
- Source: dout_2 (FF)
- Destination: dout<2> (PAD)
- Source Clock: clk_out_OBUF_BUFG rising at 0.000ns
- Requirement: 5.000ns
- Data Path Delay: 3.731ns (Levels of Logic = 1)
- Clock Path Delay: 4.523ns (Levels of Logic = 2)
- Clock Uncertainty: 0.025ns
-
- Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.050ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Clock Path at Slow Process Corner: clk_in to dout_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- W12.I Tiopi 1.037 clk_in
- clk_in
- IBUFG_u0
- ProtoComp0.IMUX.14
- BUFGMUX_X2Y9.I0 net (fanout=2) 0.987 clk_out_OBUF
- BUFGMUX_X2Y9.O Tgi0o 0.209 clk_out_OBUF_BUFG
- clk_out_OBUF_BUFG
- OLOGIC_X27Y31.CLK0 net (fanout=96) 2.290 clk_out_OBUF_BUFG
- ------------------------------------------------- ---------------------------
- Total 4.523ns (1.246ns logic, 3.277ns route)
- (27.5% logic, 72.5% route)
-
- Maximum Data Path at Slow Process Corner: dout_2 to dout<2>
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- OLOGIC_X27Y31.OQ Tockq 1.080 dout_2
- dout_2
- W20.O net (fanout=1) 0.309 dout_2
- W20.PAD Tioop 2.342 dout<2>
- dout_2_OBUF
- dout<2>
- ------------------------------------------------- ---------------------------
- Total 3.731ns (3.422ns logic, 0.309ns route)
- (91.7% logic, 8.3% route)
-
- --------------------------------------------------------------------------------
-
- Fastest Paths: TIMEGRP "dout" OFFSET = OUT 5 ns AFTER COMP "clk_in" REFERENCE_PIN BEL
- "clk_out" TIMEGRP dout_r "RISING";
- --------------------------------------------------------------------------------
-
- Paths for end point dout<1> (U22.PAD), 1 path
- --------------------------------------------------------------------------------
- Delay (fastest paths): 3.003ns (clock arrival + clock path + data path - uncertainty)
- Source: dout_1 (FF)
- Destination: dout<1> (PAD)
- Source Clock: clk_out_OBUF_BUFG rising at 0.000ns
- Data Path Delay: 1.564ns (Levels of Logic = 1)
- Clock Path Delay: 1.464ns (Levels of Logic = 2)
- Clock Uncertainty: 0.025ns
-
- Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.050ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Minimum Clock Path at Fast Process Corner: clk_in to dout_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- W12.I Tiopi 0.321 clk_in
- clk_in
- IBUFG_u0
- ProtoComp0.IMUX.14
- BUFGMUX_X2Y9.I0 net (fanout=2) 0.265 clk_out_OBUF
- BUFGMUX_X2Y9.O Tgi0o 0.059 clk_out_OBUF_BUFG
- clk_out_OBUF_BUFG
- OLOGIC_X27Y40.CLK0 net (fanout=96) 0.819 clk_out_OBUF_BUFG
- ------------------------------------------------- ---------------------------
- Total 1.464ns (0.380ns logic, 1.084ns route)
- (26.0% logic, 74.0% route)
-
- Minimum Data Path at Fast Process Corner: dout_1 to dout<1>
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- OLOGIC_X27Y40.OQ Tockq 0.336 dout_1
- dout_1
- U22.O net (fanout=1) 0.190 dout_1
- U22.PAD Tioop 1.038 dout<1>
- dout_1_OBUF
- dout<1>
- ------------------------------------------------- ---------------------------
- Total 1.564ns (1.374ns logic, 0.190ns route)
- (87.9% logic, 12.1% route)
复制代码
就不明白为什么dout【1】和dout【2】的结果差异这么大？如何可以让这一组数据约束出来结果差不多呢？ |
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2013-1-9 18:02:51
楼主