.def文件如何转换成Verilog-A文件

liufengchun100 · 发表于 2012-12-9 18:50:43

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仿真出现错误：
FATAL (VACOMP-2096): File '/home/Cadence/../models/spectre/res.def' does not appear to be a valid Verilog-A file. In previous releases, '.def' was a file extension typically used for SpectreHDL files but SpectreHDL is no longer supported. If this file is a SpectreHDL file, you need to replace it with an equivalent Verilog-A file.

目前没有替代文件可用，.def文件能否直接转换成Verilog-A文件呢，可以的话转换成什么格式？或者用Verilog-A语言重新描述一遍？请指点~~
用的MMSIM7.2