NO.108-Staff/SeniorDFT engineers（Shanghai）

kthr

Job Description:
Ø        Responsible for chip DFT architecture definition and DFT specification generation and review
Ø        Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design
Ø        Generate DFT related timing constraints and work with backend for timing closure
Ø        Provide test vectors for ATE ,Participate in ATE bring-up and debug the DFT patterns on ATE.
Ø        Develop high-coverage DFT scheme, DFT methodology ,Evaluate and establish the advanced DFT tools and flow.

Job Requirement:
Ø        Minimum BS in EE, MSEE degree preferred with 3+ years of experience in chip test
Ø        Strong background in DFT, BIST, JTAG and ATPG.
Ø        Experience with either Mentor DftAdvisor/Fastscan or Synopsys TetraMax
Strong logic Design and verification background with experience in STA.
Ø        Track record of delivering DFT solutions for SoC chips from concepts to tapeout.
Good English communication skills and teamwork sprit
Ø        Programming in Perl, tcl and c++ is a plus

KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.

If you interested in the job, pls sent your cv to: hr@kthr.com, thanks!