后端工具列表

semico_ljj

后端工具列表  详细地址：

http://ecat.edacafe.com/product_list.php?category_id=1000048

ASIC and IC Design : IC Physical Design Tools
Vendor Name Click for Profile	Product Name Click for Datasheet	Product Description
Advantest Technology Solutions Corp.	"Flexible Platform" T2000	Innovation never stops. And, with SoC devices demonstrating increasingly shorter life spans, chipmakers now have a cost effective alternative to purchasing new ATE platforms every 2-3 years, or with each new generation of device. The T2000 enables you quick access to high-volume markets with minimum investment. T2000 - "Innovative Solutions for Changing Needs"
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AMI Semiconductor (AMIS)	AMIS-39100 Octal High Side Driver	The AMIS-39100 is a general purpose integrated circuit (IC) with eight integrated high side (HS) output drivers. The device is designed to control the power of virtually any type of load in a 12V automotive environment, such as transistor gates, relays, LEDs, etc.
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Analog Bits	DLL Technology	Digital IC’s that interface to high speed memory interfaces such as DDR/QDR receive data and strobe clocks simultaneously. In order to ensure timing and guarantee data-capture, the incoming clocks need to be phase adjusted, typically by 90 degrees. In addition, the strobe clocks appear non-continuously as a method of reducing switching power and hence will require a clock system generation macro to rapidly generate clocks. Analog Bits DLL macro generates a 90 degree delayed clocks (optionally 180 or 360 degrees) from noncontinuous clock strobe. The macro also has a built-in stop capability that allows powering down the analog portions when the incoming clock is idling saving power. Additionally the macro has the ability to perform rapid re-start the clocks with the incoming clocks. The macro is also provided with programmable gate-delays which can be used to compensate for external data-path or clock-tree delays. The DLL uses our proprietary architecture proprietary ESD structure that uses core devices only, and resides inside the IO ring of two analog power supply pads, occupying no core area. The DLL macros fit into any standard IP pad pitch and can also be integrated to any custom IO rings.
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Analog Bits	Video Capture PLL	Analog Bits Video Capture PLL macro is designed for applications that require precise clock generation from a highly noisy and low frequency input pulses, such as video slave and HDTV SoC. The core operates at a maximum pixel clock rate of 160MHz and uses only core devices and hence can be easily integrated into a digital SoC. The core is fully self-contained integrating all the required circuitry for generating a high-quality phase-variable pixel stream from a mediocre quality Hsync. In addition all of the required isolation from the digital section is incorporated to maintain the highest level of noise immunity. The PLL uses a system reference clock (e.g. 14.318MHz crystal) as a high precision time reference. The PLL utilizes a high-precision 28-bit digital frequency synthesizer, with a programmable all-digital loop filter making it possible to generate an output clock with less jitter than the typical Hsync reference, enabling the production of pixel clocks superior to that of an external analog PLL. Typical power consumption of the core is150mW at 135MHz pixel rate. The core is also designed with programmable power adjustment to allow for power vs. performance tradeoffs.
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Ansoft Corp.	HFSS	HFSS is the industry-standard software for S-parameter and full-wave SPICE extraction and for the electromagnetic simulation of high-frequency and high-speed components. HFSS is widely used for the design of on-chip embedded passives, PCB interconnects, antennas, RF/microwave components, and high-frequency IC packages.
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Ansoft Corp.	Nexxim®	Nexxim® is an advanced, frequency- and time-domain circuit simulator for engineers designing the next generation of high- performance DigitalRF CMOS ICs, GaAs/SiGe RFICs, SIP/SOC packages, power delivery systems and gigabit computer and communication backplanes. Dynamic, parameterized co-simulation with HFSS™ and Ansoft Designer® enables Nexxim to combine transistor-level detail for complex and highly nonlinear circuits with full-wave S-parameter models of the interconnect to provide the most accurate simulation capability for signal-integrity analysis and RF design.
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ARM Inc	Memory Generators	ARM offers IC designers a wide range of choices from its broad portfolio of Artisan memory products. The Artisan high-performance, high-density, low-power and ultra low-power memory generators are optimized for each silicon technology. ARM's Artisan Process-Perfect™ Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields. Each product is delivered with a complete set of views and models for leading EDA tools.
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ARM Inc	Standard Cells	ARM's Artisan standard cell libraries are developed using its Artisan Process-Perfect™ Design Methodology and based on feedback from customers, EDA, IP, design services and foundry partners. The result is a widely-used set of libraries that offer a wide range of performance and density choices. The Artisan SAGE-X™ Library offers an optimal mix of density and speed that is well suited for mainstream applications. The SAGE-HS™ and SAGE-NHS High-Speed Libraries complement the SAGE-X Library by offering solutions for speed critical designs. Each product is delivered with a complete set of views and models for leading EDA tools.
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Cadence Design Systems, Inc.	Cadence Chip Optimizer	Silicon-proven, full-chip physical design optimization system that improves manufacturability, yield, and performance, thus addressing the ever-important requirements for shorter time to convergence and shorter time to volume. It optimizes layout based on electrical constraints, manufacturing rules, and objectives. Operating Systems: Sun, AIX, Linux
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Cadence Design Systems, Inc.	Virtuoso Layout Migrate	The physical layout migration tool that supports fast process and design rule migration of hard IP, custom digital designs, mixed-signal blocks, memories, and standard cell libraries. Operating Systems: Sun, HP, Linux
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Cadence Design Systems, Inc.	Virtuoso NeoCell Analog Physical Synthesis	Translates analog cell schematics into a full-custom optimized layout and capture the subtle electrical and geometrical constraints to enable analog layout reuse. Operating System: Sun, HP, Linux
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Cadence Design Systems, Inc.	Virtuoso NeoCircuit Circuit Sizing & Optimization	Performs automatic circuit sizing and optimization for custom digital, RF, and mixed-signal circuits -- employs the designer's simulator of choice to size, bias, and verify circuits interactively. Operating Systems: Sun, HP, Linux
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Cadence Design Systems, Inc.	Virtuoso® Chip Assembly Router	A constraint- and design-rule driven interactive and fully automatic shape-based router. It supports block authoring and chip authoring solutions for designs at any level of the hierarchy. Operating System: Sun, HP, AIX, Linux
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Cadence Design Systems, Inc.	Virtuoso® Chip Editor	The center piece of the full-chip integration function, it provides high-performance editing for full-chip finishing tasks and the capacity to handle your largest designs. Operating Systems: Sun, HP, AIX, Linux
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Cadence Design Systems, Inc.	Virtuoso® Layout Editor	The industry-standard base-level custom physical layout tool, it supports the physical implementation of custom digital, mixed-signal, and analog designs at the device, cell, and block levels. Operating Systems: Sun, HP, AIX, Linux
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Cadence Design Systems, Inc.	Virtuoso® Layout Editor Turbo	The mid-range custom block authoring physical layout tool, it supports the physical implementation of custom digital, mixed-signal, and analog designs at the device, cell, and block levels. Operating Systems: Sun, HP, AIX, Linux
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Cadence Design Systems, Inc.	Virtuoso® Schematic Editor	The design composition environment that delivers an extensive set of tools for custom IC design entry, from architectural definition to final structural implementations at the transistor level. Operating System: Sun, HP, AIX, Linux
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Cadence Design Systems, Inc.	Virtuoso® XL Layout Editor	The high-end custom block authoring physical layout tool that supports the physical implementation of custom digital, mixed-signal, and analog designs at the device, cell, and block levels. Operating System: Sun, HP, AIX, Linux
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CebaTech Inc.	IP Technology	The communications (networking and storage) industry is migrating to 10Gbps rates for servers and routers, transport offload engines to address latency and software overhead, iSCSI based network attached storage, security based on IPSec/IKE and mandatory packet filtering for firewalling. Over the past decade, communications developers have implemented these protocols in software, relying on a combination of embedded processors, highly optimized code, and massive memory to handle performance limitations. Although processor performance continues to improve, developers must increasingly look to hardware-based implementations to achieve continuous gigabit and especially 10Gbps throughput.
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Cubic Wafer	Hybrid IC	Hybrid integrated circuits are devices that apply standard semiconductor processing technology to individual ICs, and fuses the ICs together to simultaneously form an electrical, mechanical, and thermal bond. By applying semiconductor processing techniques to the packaging world, hybrid ICs realize the advantages of semiconductor processing. Advantages, such as extremely small and high density interconnects, lower cost, lower power, and scalability are all realized with Cubic Wafer’s patented hybridization process.
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Denali Software, Inc.	Blueprint	Blueprint is used by chip design teams to automate the creation and management of control registers, and all related models, design views and documentation. From a register description language (RDL) input, Blueprint generates views for hardware and software development, verification, and documentation. Supported output formats include Verilog, C, C++, OpenVera, e, OVL, Frame, HTML/XML, Word and more
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Design Workshop, Inc.	DW 2000	Custom IC Layout Tool for Digital, Analog and Deep-Submicron designs that includes a powerful scripting language Max. Metal Layers: 256 IC Types: Full Custom Special Routing Abilities: none Output File Formats: JEOL-52, Mebes, JEOL-01, Gerber, Cambridge SPD, GDS II Design Checking: HLE, DRC, LVS Operating System: HP-UX, MacOS, Solaris, Windows 98, Windows NT
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Dini Group	Phar Lap TNT DOS Extender	A DOS Extender is a software tool that enables developers to access extended memory beyond the 640K DOS limit. The DOS extender functions as a layer between DOS in real mode and an application in protected mode. It is embedded into the program and is invisible to the end-user. Phar Lap's DOS extenders support all the major industry standards-DPMI, XMS and VCPI-so that Extended-DOS applications can run under DESQview™ and all modes of Windows™, as well as DOS.

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Magma Design Automation, Inc.	Blast Plan Pro	Blast Plan™ Pro is a complete, hierarchical design planning and prototyping solution that is fully integrated into Magma’s RTL-to-GDSII flow to enable designers to manage the complexity of multimillion-gate designs and reliably achieve timing closure.
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MOSAID Virtual Silicon	Memory Compilers and Instances	Today's system-on-chip designs require many configurations of embedded memories' size, aspect ratios, and testing options. "What-if" scenarios are easy to explore using the RAM and ROM compilers, helping designers to perform optimal floorplanning of the design. System designers can evaluate early architectural tradeoffs between performance, area and power by easily varying the aspect ratios, word depths and word widths of their designs. Once satisfied with the resulting configuration, the compiler will create all the EDA model views necessary to drive today's most popular IC design software. All of the SRAM memory compilers provide edge-triggered synchronous read/write operations, byte write capability, and zero hold time for synchronous inputs. Fully static design provides low voltage data retention, operation down to 0Hz, and zero standby current. SRAM and ROM memory compilers support scan and built-in-self-test (BIST). 1 Port SRAM Compiler Two Port SRAM Compiler Dual Port SRAM Compiler ROM Compiler Multi Port Register File Instances Custom Instances
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MyCAD, Inc.	LayNet Pro	Multi-Level Hierarchical Layout Extraction Hierarchical Labeling Extract standard SPICE and HSPICE format with model names Automatically locates any device and net Dracula Command Compatible
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Optimal Corp.	O-Wave™	O-Wave™ is the fastest high-speed, high-accuracy 3-D full-wave extraction tool on the planet. Only O-Wave can accurately analyze complex high-frequency IC, package and PCB models for true IC-Package-PCB co-design.
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Optimal Corp.	PakSi-TM™	PakSi-TM™ allows package engineers to save time and money by determining the thermal characteristics of the IC package before committing the design to fabrication.
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Optimal Corp.	PowerGrid™	PowerGrid™ is a unique suite of DC and AC power delivery tools for IR drop and ground bounce analysis for IC packages and printed circuit boards ( PCBs).
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Pulsic Limited	Unity	High performance shape based auto-interactive IC physical design solution for analog, custom, digital, mixed-signal, embedded DRAM/SRAM and system-on-chip (SoC) design - incorporating solutions for ECO placement, routing, timing closure, signal integrity and power routing.
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Sagantec	Anaconda	Anaconda is a schematic-driven, constraint-based compaction tool that accelerates analog physical design by automating repetitive manual layout tasks and enabling analog design reuse. From an easy-to-use and powerful graphical user interface, designers can add constraints in both schematic and layout views thereby annotating the design database with design intent. Anaconda then automatically updates the layout according to schematic device parameters and additional design constraints to create a refined and final DRC and LVS correct layout. Output File Formats: GDSII or CIF
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Sagantec	SiClone	SiClone accelerates physical implementation and closure for full-custom design. It enables simultaneous, n-level hierarchical layout compaction, process migration and physical optimization. Output File Formats: GDSII or CIF
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Sarnoff Europe	TakeCharge® Design Kit (TDKx)	The TakeCharge® Design Kit (TDKx) is a total ESD design and layout solutions package, either off-the-shelf and ready for selected foundry processes, or customdeveloped for a proprietary process and/or a custom application set. Upon delivery, the TakeCharge® Design Kit is ready for company distribution to the I/O and IC design and layout engineers.
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Sequence Design, Inc.	CoolPower (Next-Generation PhysicalStudio)	Power Integrity Closure for Nanometer SoC Design CoolPower™ is the industry's leading cell-based Power Integrity solution for concurrent optimization of power, dynamic voltage drop, timing and signal integrity (SI) for nanometer SoC design. CoolPower predicts and corrects design closure issues both before and after routing. It gives users the ability to interactively optimize hierarchical, multimillion gate SoC designs at the block-level, as well as, full-chip level. CoolPower integrates into popular third-party place and route tools to enable existing physical flows to reach fast, predictable design closure in silicon geometries below 130 nanometers (nm). COOLPOWER HIGHLIGHTS Power Gating Achieves faster design speeds while maintaining longer battery life Complete power gating solution creates, optimizes, and verifies powergated designs Voltage Drop Optimization Intelligent voltage drop optimization reduces leakage power and increases yield Automatically fixes dynamic voltage drop problems using decoupling capacitance insertion and peak power spreading techniques Total Power Optimization Reduces static leakage power and dynamic power Concurrent analysis preserves timing and signal integrity Timing & Signal Integrity Optimization Pre-route creation and post-route repair reduces iterations Netlist and placement changes optimize timing, signal integrity, and voltage drop impact on timing Hierarchical Top-level Optimization Register-bounded methodology improves accuracy and increases capacity while reducing run-time Single-pass, push-down approach increases design performance and eliminates design iterations General Integrated CoolTime concurrent analysis engine eliminates convergence problems Seamless integration with standard physical design flows and formats Easy-to-use graphical interface and detailed analysis reports
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Sequence Design, Inc.	CoolTime	Electrical Integrity Analysis for Nanometer SoC Design CoolTime™ is the industry's leading cell-based electrical integrity solution for concurrent analysis of voltage drop, power, electromigration (EM), timing and signal integrity (SI) for nanometer SoC designs. Eliminating the need for multiple point tools and iterations, CoolTime renders accurate and convergent analysis of inter-dependent electrical effects. CoolTime shares a common platform with CoolPower™ optimization to ensure rapid design closure for dynamic voltage drop, leakage power, EM, timing and SI effects. COOLTIME HIGHLIGHTS Highest accuracy, capacity and performance SoC tool for dynamic voltage drop analysis Comprehensive RLC model including decaps and package Simulation-based and vectorless modes for realistic stimulus High-speed embedded extractor using silicon-proven Columbus™ technology Cell characterization for transient current waveforms, Accuwave™ Accurate memory and macro current modeling Event-based timing and SI analysis for crosstalk and voltage drop effects Hierarchical analysis providing SoC capacity Cell characterization for voltage-aware timing and SI modeling 5-10x faster than existing STA tools Virtual rail voltage and recovery time analysis for MTCMOS power gated designs Easy-to-use graphical interface and detailed reports Shared analysis platform with CoolPower optimization Correlated with silicon and industry standard circuit simulators
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Sequence Design, Inc.	ESL Power Technology	Sub 90nm technology makes it possible for SoC architects to put more IP onto their chips. Chips now have microprocessor and DSP cores communicating with custom IP and memories via multiple busses on a single die. The challenge facing design teams is to conceive and implement the optimal chip architecture that balances performance, area and power requirements in a hardware/software platform. This balancing act is pushing design teams to explore alternate architectures at levels of abstraction higher than the RT level all the while further reducing their time to market. These two competing forces are driving leading edge teams to adopt SystemC as the Electronic System Level (ESL) design language of choice. While a number of vendors are enabling performance and area exploration in a SystemC environment, Sequence is taking the lead in tackling the power exploration problem. Technology Highlights Hardware software trade-offs for power Power exploration during system architecture design Power at ESL with 30% accuracy to equivalent gate-level Power trade-offs in an ESL synthesis flow to render optimal RTL for area, timing and power Up to 100x speedup in simulation run times to allow power exploration for true system behavior Built on top of the industry leading PowerTheater platform
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Sequence Design, Inc.	PowerTheater	Low Power Design & Power Analysis For Nanometer System-on-Chip Design PowerTheater is a comprehensive set of power tools that create maximum power efficiency for your SoC designs. Sequence is the first company delivering power software focused at the architectural, RTL and gate level. PowerTheater is a family of full-chip power tools that can be used throughout the IC design process. PowerTheater products analyze, display and help the user reduce power for the whole chip and each individual module. A combination of special-purpose estimation algorithms and carefully crafted modeling techniques ensures accuracy. PowerTheater HIGHLIGHTS SoC RTL Power Analysis - Analyze power consumption early in the design flow to check the power budget and direct power reduction efforts Low-power RTL design - Perform power analysis as RTL blocks are being designed, including Zerosim vectorless capability to perform architecture tradeoffs Flexible and easy-to-use RTL power optimization - Reduce power before synthesis where impact is greatest Handle clock, memory, data path control logic and I/O - See the simultaneous impact of all the components in a full-chip design De facto industry standard for RTL power design - High-performance, high-capacity full-chip power analysis, including peak and timebased analysis, vector coverage analysis and power optimization Complete HDL coverage for SoC design - Support for Verilog, Verilog2001, VHDL and mixed language environments in one-pass Versatile graphical analysis environment - View power analysis results and optimization trade-offs quickly, and intuitively produce the most power-efficient designs possible Accurate gate-level power verification - Provides precise assessment of chip power behavior either average or time based, including SPEF back-annotation, built-in slew calculator and support for hierarchical design flows Integration with CoolTime from Sequence - Determine the critical clock cycle for dynamic voltage drop analysis and feed forward initial starting conditions for CoolTime
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Sierra Design Automation, Inc.	Sierra Olympus-SOC	Next Generation Netlist-to-GDSII System Comprehensively Addresses Variations in Design Modes, Process Corners, and Lithography.
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Sierra Design Automation, Inc.	Sierra Pinnacle	Pinnacle suite, provides the fastest and the best design for variability implementation solution for the biggest chips.

qinze

ddddddddddddd

dmq0420

这么多!  能不能介绍几个主流的

amirjon

lsqswl

看不懂......

zollic

膜拜大神！！！

icfbicfb

别误人子弟 了好么，  上面有一半工具都用不到， 啥玩意，

tony1334

。。。。。。。

ra3d

别误人子弟 了好么，  上面有一半工具都用不到， 啥玩意，