面试被问到：增加decap会减小IR_drop，会带来什么影响？

beckdavid · 发表于 2017-6-23 12:52:08

回复 19# wink1988

主要是可以减少Dynamic IR drop，想象一下，数字器件大量翻转时或者在clock path上瞬态电流很大，这样power线上有瞬间压降，如果附近有decap，decap可以给耗电大的地方补充电流，稳定power电压

Anne_xiyuan · 发表于 2018-10-25 11:03:17

回复 5# zhangqiong137
请教Decap的工作原理。S、D接VDD,G接VSS？

supericeman999 · 发表于 2018-10-31 11:12:29

谢谢分享

Dlinkererr · 发表于 2020-5-18 18:12:44

thank u for sharing

hadeheng · 发表于 2020-11-27 18:39:15

thank u for sharing

zhangyang370281 · 发表于 2021-4-21 12:35:59

yohuang 发表于 2012-11-7 18:45
DCAP is built from MOS transistor and used mos gate cap, the gate leakage of dcap is a significant c ...

Decap单元和ESD的关系是怎么样的，好多工艺厂商检查ESD时并不检查Decap cell的ESD防护

貌不可焱 · 发表于 2022-1-18 22:32:09

感谢分享

海阔天空——飞 · 发表于 2022-11-1 18:02:05

yohuang 发表于 2012-11-7 18:45
DCAP is built from MOS transistor and used mos gate cap, the gate leakage of dcap is a significant c ...

hi, I have two questions about DCAP:1. how does Decap affect the ESD? the IO with ESD protection has rejected the ESD events, how does ESD happen inside chip?

2. for 40nm or below, the thin oxide will cause leakage from gate to source/drain, could you explain more detail about the physicl principle? or just give a link or a doc to self-learn?
thanks in advance.

sutaotao2001 · 发表于 2022-11-1 18:27:24

电容太大，充电时间变长，另外大电容的工作频率低些。小电容的resonance点会高些

sutaotao2001 · 发表于 2022-11-1 18:30:46

电容对ESD有一定的帮助。不过信号本身特殊时，频率不在范围i可能不工作。有一定的风险

[求助] 面试被问到：增加decap会减小IR_drop，会带来什么影响？

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