[EBOOK]Power Trade-Offs and Low Power in Analog CMOS ICs

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Power Trade-Offs

and Low Power in

Analog CMOS ICs

Power, accuracy and noise aspects in CMOS mixed-signal design

by

Sanduleanu, Mihai Adrian Tiberiu

and

Ed A.J.M van Tuijl

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part2

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part3

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part4

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final part

semico_ljj

再贴个目录和Preface出来！毕竟要下载这么多的东东呢！

semico_ljj

Book Description
The work presented in Power Trade-offs and Low Power in Analog CMOS ICs concerns power, noise and accuracy in CMOS Analog IC Design. In the presented material it is shown that power, noise and accuracy should be treated in an unitary way, the three terms being well inter-related. The book is divided in a theoretical part which covers sub-micron digital and sub-micron analog followed by an applicative part where accuracy related power and noise related power is encountered. The main part of the book deals with analog circuits working in a digital environment where the process has been optimized for digital applications. The general trend, in digital, to scale down the power supply makes the process of designing analog circuits a difficult task since most of the solutions valid for large supply voltages are not anymore useful due to the low voltage limitations. At low supply voltage, the key problem of analog signal processing functions is dynamic range reduction. In all cases this yields in an increase of power consumption. Besides, analog designers have to cope with second order effects generated by the incompatibility of the process with analog performance. To get the best performance, knowing the limits of power in analog circuits and clearly defining the environment where analog circuits should work is a must. Starting from fundamental/physical limits we are discussing the practical limits of power in digital, mostly at the architecture level and practical limits of power in analog at circuit and architecture level. The fundamental limits are asymptotic limits and they cannot provide realistic comparisons between possible solutions. That is why the approach here provides a step further into power analysis by discussing all possible practical specs related to power at circuit and architecture level. For analog circuits Dynamic-Range*Speed product is limited by power, topology and supply voltage regardless of the type of circuits: continuous time or sampled data, current-mode or voltage mode.

Product Details

• Hardcover: 160 pages
• Publisher: Springer; 1 edition (March 31, 2002)
• Language: English
• ISBN: 0792376420

[ 本帖最后由 semico_ljj 于 2006-12-14 09:42 编辑 ]

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Table of Contents(Page_1)


Selected Symbols and Abbreviations
CHAPTER 1  Introduction
1.1. Motivation
1.2. Problem definition
1.3. Scope and outline
REFERENCES
CHAPTER 2  Power considerations in sub-micron digital CMOS
2.1. Introduction
2.2. Fundamental limits
2.2.1. Thermodynamic limit
2.2.2. Quantum mechanics limit
2.3. From fundamental limits to practical limits of power. An architecture level
approach
2.3.1. Power in FIR filters
2.3.2. Power in IIR Filters
2.4. S/N ratio and power in fixed point applications
2.5. Adders and computational power
2.5.1. Ripple carry adders (RCA)
2.5.2. Cascade adders
2.5.3. Chain versus tree implementations of adders
2.6. Ways to low-power in digital
2.6.1. Process technology
2.6.2. Logic and circuit level
2.6.3. Power reduction at architecture level
2.6.4. The algorithmic level
2.6.5. Power at system level
2.7. Example of a digital video filter
2.8. Conclusions
REFERENCES
CHAPTER 3  Power considerations in sub-micron analog CMOS
3.1. Introduction
3.2. Process tuning towards digital needs. Consequences on analog
3.2.1. Transconductance
3.2.2. Output conductance
3.2.3. Difussion and gate capacitances
3.2.4. Accuracy
3.2.5. Speed
3.2.6. Substrate noise

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amswu

书不错，非常感谢！

pickpunk

好书一本啊