[EBOOK]Power Trade-Offs and Low Power in Analog CMOS ICs

cheny1982

cheny1982

zhbzf2003

DASDFDF

ahhuh

值得收藏的书，谢谢分享。

ahhuh

some of the trade off of design that we must know

ryanbowen40

书不错，非常感谢！

jerry1

要看看了！~~

jerry1

不过现在穷啊！

semico_ljj

The main part of this thesis focuses on power, noise and accuracy of analog circuits. However,
the working environment for the analog circuits treated here is a mixed level environment. To
get the best performance, knowing the limits of power in digital and clearly defining the
environment where analog should work is a must. In sub-micron digital CMOS, to optimize
power dissipation, a low-power methodology applied at different levels of abstraction is
necessary. Power in analog is related to noise and accuracy. A further investigation to
quantify their inter-relationship is required. When accuracy is important, new solutions of
increasing accuracy in modern CMOS have to be found. We are looking for solutions
insensitive to second order effects like mobility reduction and velocity saturation capable of
working at low voltage with high linearity, dynamic range and accuracy, with low-power
consumption. The outline followed in this thesis is described below:

semico_ljj

[1] N. Weste, K. Eshragian, " Principles of CMOS VLSI design", Reading MA, Addison Wesley,
1985.
[2] J.S. Ward et al., "Figures of merit for VLSI implementations of digital signal processing
algorithms", Proc. Inst. Elec. Eng., vol. 131, part F, pp.64-70, Feb. 1984.
[3] M. Kahumu, M. Kinugawa, "Power-supply voltage impact on circuit performance for half
and lower submicrometer CMOS LSI", IEEE Trans. Electron Devices, vol.37, n0.8,
pp.1902-1908, Aug. 1990.
[4] M. Nagata, "Limitations, innovations and challenges of circuits and devices into
half-micron and beyond", Proc. Symp. VLSI circuits, pp.39-42, 1991.
[5] J. Borel, "LP/LV circuits in the deep submicron era" in the Proceedings of the 2nd
IEEE-CAS Region 8 Workshop on Analog an Mixed IC Design, Baveno, Italy, 1997.