【社招】LSI中国2012年7月27职位更新

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1.
SerDes Field Coreware Engineer  -Shanghai（1个）

Job Description

The Field Coreware Engineer is a challenging and cutting-edge position with responsibilities to work closely with LSI internal IP development, foundation IP, methodology, and design center engineering/development teams to support complex ASIC designs. This position will support LSI/3rd Party IP for customer ASIC and internal ASSP designs providing “Best in Class” support

Strong communications skills are important for this position. This is a position for developing and honing verbal and written communication skills, and for interfacing to many different people and engineering organizations within and external to LSI. Position requires regular interface with LSI customers. A successful candidate will have a strong design background, debug skills, good scripting skills, and hands on experience with IP integration. This position will require travel and onsite support at times at the customer site.

Requirements/Qualifications (Education)

- 5-10+ years experience as an application, design or development engineer

- Experience developing IP or integrating/implementing IP in an SOC (System on Chip)

- Prior experience with RTL coding and verification a plus

- Knowledge in one or more of the following IP:

o SerDes

o Memory IF: DDR, etc,

o Protocol IP : PCIe, Ethernet (example: 10G-KR4), etc…

o Processors/Subsystems

o SOC interconnect: AMBA, etc.

- Must have the ability to understand Specifications

- Experience with EDA tools such as Simulators (Synopsys VCS, Cadence NC-Verilog, Mentor ModelSim), Synopsys IC Compiler, Synopsys PrimeTime SI

- Understanding of the ASIC Design Flow

o Design Closure STA (Static Timing Analysis) Constraints

o Simulation/Debug

o Basic understanding of DFT (Design for Test)

o Basic Understand Power Estimation & Optimization

- Experience Debugging Simulations

- Basic Understanding of System Architecture/Applications

- Prototyping/Emulator knowledge a plus

- Soft/People Skills:

o Customer support skills (Communication, Positioning etc.)

o Issue Solving

o Conflict Management

- Willing to learn, expand horizons

- Positive attitude and ownership taking a must

2.

ASIC Customer Design Engineer-Shanghai（若干）

Job Description

- LSI Corporation offers an excellent opportunity to contribute to a team environment and to grow personal career path. You will be working with internal and external customers to develop state of the art IC solutions utilizing LSI's leading edge CMOS cell-based ASIC technologies. You will have responsibility for ASIC designs through all of the key development and implementation phases including RTL analysis, synthesis, design optimization, timing verification, simulation, test insertion, physical design, vector generation, and post-prototype test support. Candidates will have opportunity to work on the latest 40nm/28nm designs.

Detail design tasks include

- Presales support (die size support, memory generation, addressing customer questions and concerns.)

- RTL analysis & synthesis

- Top level and block level physical design Implementation (bonding, floor planning, power structure insertion, place and route, timing closure)

- Test structure insertion/silicon testing debug

- Formal verification

- Static timing analysis

- Cross talk analysis

- Power verification

- Physical verification

- Overtime, candidates are expected to develop the most of above skills. Candidates who have the desire to seek the in-depth and broad technical challenge should apply.

Requirements/Qualifications (Education)

Education: BS/MS Electrical, Computer Engineering or Equivalent

- 2+ years experience in ASIC design and implementation. Familiar with all aspects of ASIC design implementation flow and specializing in physical design or DFT implementation. The ideal candidate should have successfully completed at least one mid-size ASIC or ASSP tapeout.

- Experience with Synopsys Astro or ICC is a plus. Other physical design tool experience will also be considered. Scripting skill is a strong plus.

- Experience in debugging prototypes considered a strong plus. Knowledge and hands on use of test insertion / vector generation / verification a plus. Some experience with Signal integrity a bonus.

- Experience in working with customers is desired. Must possess excellent communication skills and strong self-motivation. Be able to effectively communicate with other members of the design team, supporting organizations, and management. This position requires frequent interface with LSI customers

- Candidates have ONE OR MORE good skill sets of the following areas are highly encouraged to apply:

- RTL Analysis/Synthesis/STA: The ideal candidate should have strong skills for the front-end of design

- implementation which includes RTL Analysis, Synthesis Strategies, and STA setup for complex ASIC

- environments. This would include strategies for power management.

OR

Physical Design Implementation: The ideal candidate should be strong in the Physical Design (at least at block level) which includes floor planning, design closure, & STA. Having strong DRC & LVS skills are a plus. Strong

- Synopsys Astro/ICC experience a plus. Having Mentor Calibre skills a plus.

- OR

- Physical Verification: The ideal candidate should have in-depth understanding of transistor level IC fabrication process, familiar with major foundries(TSMC or SMIC) runsets and verification flow, custom layout experience is a plus, successfully done LVS/DRC/ERC/Antenna check for multiple tapeouts is a strong plus. Understanding of DFM is a plus. Calibre experience is a plus.

- OR

- DFT: The ideal candidate should be strong in all DFT (Design for Test) for all aspects. This would include

- scan/TDF, TestKompress, MEMBIST/BISR, JTAG and etc. Having STA skills is a plus for all aspects of test. Responsible for support / debug of customer designs after delivery of prototypes

3.
Digital Design Engineer-Shanghai （若干）

Job Description

- Candidates for this position should have experience in the design and design management of large, high-speed, mixed signal SoCs. The designs must have contained a variety of both hard and soft-macro IP blocks. The candidate should be an expert in all parts of the SoC flow from IP deliverable hand-offs (in RTL or gate), to synthesis, DFT and test insertion, floorplanning, P&R, timing closure, signal integrity, power analysis and verification. After at least 5 years of design experience the candidate should have 3 years of design management experience. MS or higher degree in EE is required.

Requirements/Qualifications (Education)

- MSEE or higher degree in EE required.

4.
Firmware Engineer-Shanghai（若干）

Education and Experience Requirements

BS in Electrical Engineering, Computer Science, or Computer Engineering is required with 6+ years of firmware development.

M.S. preferred with 4+ years in firmware development.

Knowledge, Skills, and Abilities

-
Must demonstrate expertise in design and implementation of event-driven, real time firmware solutions using C/C++ programming

-
Must be able to work with ASIC and software engineers in a collaborative environment

-
Quick learner with high level of self-motivation and dedication, with ability to deliver high quality products on time

-
Must have an excellent computer science background and demonstrated strength in designing efficient embedded firmware for storage or networking products

-
Firmware/System debug skills utilizing debugger, protocol analyzer is required

-
Good understanding of RTOS concepts including task switching, deadlocks, and resource management issues is required

-
High level of skill in problem recreation, trapping and resolution, possess good written and verbal communication skills.

-
Communicate effectively in a team, able to multitask effectively in fast-paced environment.

-
Understanding of NAND Flash concepts, knowledge of Flash management techniques, including wear leveling, garbage collection (optional but strong plus).

-
Knowledge and hands-on experience with storage protocols is preferred (SAS / SATA)

5.
Read Channel Emulation Engineer-Shanghai（若干）

Job Description

- The successful candidate will be responsible for verification and the associated design works(synthesis and Place&Route) on the FPGA and Palladium platform.

- Some design for peripheral logic but mainly verifying the blocks within a System on a Chip design. This will include the documentation of test plans and procedures.

- The candidate must be familiar with FPGA design flow.

- Candidate should be proficient in verilog design language and ASIC & FPGA CAD tools.

- Teamwork and good communication skills are critical

- Perl, Matlab, and C language and systems engineering skills is a plus

Requirements/Qualifications (Education)

- Education: BSEE or MSEE with 5+ years experience.

6.
Read Channel Verification Engineer-Shanghai（若干）

JOB DESCRIPTION:

As a member of the Read Channel team, candidate must be willing to work as an extended

member of the design team. Duties will include functional verification of Storage read

channel mixed-signal IP. Candidate will be expected to contribute to design and development

of System Verilog based verification environment and will be responsible for verification

closure of block/chip/system level functions for mixed signal based IP. Experience with

System Verilog and functional coverage methodologies are required. Must be willing to

follow a disciplined verification methodology and to work closely with a multi-location,

international design team. Excellent teamwork and communication skills are required.

PREFERRED EXPERIENCE:

BSEE with 3-5+ years of design and/or verification experience required, MSEE preferred.

Required knowledge and skills:

- Expertise in System Verilog required

- Good understanding of Digital Signal Processing

- Good understanding of Analog and Digital Circuits

- Very good analytical/debugging skill

- Good verbal and written communication skills

Desirable skills:

- Knowledge of Verilog-AMS, Perl

- Knowledge of verification methodologies including functional coverage and constrained

random testing

- Knowledge of VLSI design flows & DFT

- Familiarity of high level programming language

- Experience working with globally distributed team

7.

HDD Read Channel Architect -Shanghai（1个）

Job Description

- We are looking for an engineer with a track record of excellent performance to join our read channel architecture team. In this role you would be part of a dedicated team developing LSI's leading hard disk drive ASIC technology.

- This job spans the invention process from the conception of a new idea, through reduction to practice in software, close collaboration with design teams and verification of the design through to validation of performance through bench testing. In your role you will with work closely with Design and Verification teams in Shanghai and with the RC Architecture team in the United States.

- Our core requirements are a deep knowledge of digital communications technology; familiarity with detection and coding for magnetic recording; some experience implementing signal processing and detection algorithms in software and good programming skills in C/C++ and scripting languages. Experience with design verification and bench testing would both be very desirable.

Requirements/Qualifications (Education)

- PhD in Electrical Engineering or equivalent. Deep knowledge of the principles of digital communications. Familiarity with signal processing and programming

8.

Test Operations Engineer -Shanghai（若干）

Job Description

- To support new product introduction into subcontractors and facilitate high volume ramp

- Manage execution deliverables covering test programs and all the essential test hardware and co-work with supply chain management to meet/exceed on time deployment at subcontractors

- Drive KPIs at subcontractors to meet/exceed LSI performance metrics expectations

- Drive cost reduction and margin improvement initiatives to achieve the manufacturing cost objectives

- Support new technology/best practices evaluation/assessment, early adoption and introduction into subcontractors

- Ensure test process compliance to prevent manufacturing execursions

- Ensure compliance of quality requirements at subcontractors

Requirements/Qualifications (Education)

- University graduate (EE degree) with 5 years or more in product, test, and high volume manufacturing operations experiences in the semiconductor area

- Solid background in high speed digital and mixed-signal testing is essential

- Working experiences with ATE andancillary test equipments. Teradyne Catalyst/UltraFlex, Advantest T2000, Delta/Seiko Epson handlers and TEL/Accretech/Opus probers will be of advantage

- C++ and/or Perl programming skills

9.

Test Engineer -Shanghai（1个）

Job Description

- To support prototype and production releases of new products. Manage debug of test program, design and debug of test hardware, and meet product release schedule.

- Support test program development for implementing changes in new test methodologies for test coverage improvement.

- Pursue Design for Test initiatives to optimize testability and achieve test cost reduction via test time reduction and multiple site test solutions for production release

- Support test chip test development and characterization of new IP used in LSI products.

Requirements/Qualifications (Education)

- University graduate students with top scores in GPA

- Prior working experiences in the semiconductor industry field, specially in either IDM, Fabless, or Foundry environment

- ATE programming skills would be essential ,

- C++ and/or Perl programming skills

-T2000 platform using experience is must

10.

Systems Application Engineer(RSD) –Shenzhen（若干）

Job Description

Provide product support for customers that use LSI’s I/O standard products. Product support involves helping the customer with the initial integration of the I/O standard product and debug of any software or hardware issues that arise. Work with the technical publications group on data manuals, systems engineering notes, and other documentation support. Provide training for customers and the Field Application Engineering organization. Work with the development engineering departments, hardware and software in debugging and supporting new products. Also involves working with silicon and software in a system environment

Requirements/Qualifications (Education)

- Considering candidates with BSEE/BSCE. 5+ years of experience required.

- The ideal candidate will have a technical understanding of SAS, SCSI and PCI Express. Candidate will have embedded firmware debug experience and posses systems level knowledge. Good communication/interpersonal skills and the ability to listen and incorporate feedback is essential. The ability to handle multiple tasks at the same time is also required.

- C coding experience or equivalent coursework required.

- Logic analyzer, oscilloscope and protocol analyzer experience a plus.

11.
Program Managers-Shenzhen（1个）

Scope of programs:

- International Programs with contributors from several organizations and/or Business Units
- Programs with high business impact, above $20Mio total over product lifetime
- Programs with high development cost and effort, above 5 man years
- Programs with concurrent engineering of customer product and IP customization

Responsibilities:

- Project Definition:
Ensure that Goals, Objectives & Scope for the Program is defined, understood and agreed to
Work with engineering and management to form the project team.

Develop a Project Plan with clear ownership and deliverables milestones together with LSI and Customer teams
Work with engineering to calculate and forecast the effort and investment for successful project execution
Drive concurrent Risk Management as integral part of the project planning and execution

- Project Execution:

Call regular project review meetings, internal and with the customer

Coordinate and align the customer execution with internal LSI organizations and deliverables.

Ensure effective communication between all parties involved
Provide regular project reports (to the customer and internal)
Continuously track/maintain and measure project schedule progress against plan
Perform continuous Risk Management and elevate critical issues and risks.
Manage the Change Management Process (with the customer and internal to LSI)
Manage the Action Management Process
Facilitate Project Lessons Learned (internal and with the customer)

- Requirements:

Minimum 5 years experience in the fields of management, sales/marketing and engineering

Good understanding of the ASIC design process & methodology
Detailed knowledge of project management methodology, processes and tools
PMI certification is a plus
Expert knowledge in Microsoft Project, Excel, and Outlook
Basic knowledge in Microsoft Word and PowerPoint
Engineering degree or equivalent
Ability to adopt and execute a structured working methodology

Fluent verbal and writing language skills in native language and English

Strong communication skills
Excellent interpersonal and leadership skills
Self motivated and self driving