浦东/浦西大型美资公司+Senior/Staff Verification Engineer

chloe-zhang

1.产品：IP
地点：浦东
Lead Verification Engineer        
     Position Description:
Ø  Deliver/implement advanced verification solutions by utilizing Cadence’s Incisive Verification product portfolio. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.
Ø  Specific duties include:
Ø  Deep understanding on ASIC design and verification flow
Ø  Excellent knowledge of advanced verification methodology like eRM/OVM/UVM/VMM
Ø  Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM)
Ø  Proficiency in System Verilog, System C and/or e (Specman)
Ø  Developing and using Verification Components (eVC, OVC,UVC,VIP)
Ø  Developing and using assertion based verification and formal analysis methods
Ø  Skilled in scripting language, such as Perl, C shell, Python, Make file
Ø  Assessing the project verification requirements

     Position Requirements:
Ø  BS degree with 4+ years of applicable experience, MS degree with 2+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.  
Ø  Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English.
Ø  Will have demonstrated hands-on experience and expertise with Cadence verification design tools or equivalent tools, flows and methodologies required to execute a verification project.
Ø  Will have demonstrated successful completion of 3+ verification projects as an individual contributor
Ø  Will have DDR project verification experience


2.产品：高速接口
   地点：浦东

Logic Design Engineer

Responsibilities:

XXXLogic Design Engineer is working on cutting-edge Digital and Mixed-signal IP development for XXX worldwide clients, including High Speed Serial Links, Protocols, Memory Interface, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm and beyond, you will be participating in the front-end logic design or mixed signal design.

Requirements:

1. ME/EE/CS or background in related areas.

2. Research and/or development experience in one or more of the following areas:

·
Logic Design on the basis of the target system specification

·
Mixed-signal model design on advanced technologies

·
Proficiency in programming and/or scripting languages is a plus

·
Knowledge on Protocols, High Speed Serdes or DDR is a plus

3. Experience in one or more of the following application domains, is a plus

·
High performance computing system, processor, chipset and ASICs

·
High end communication, networking, mobile and data center applications

·
Digital signal processing, sensor and Internet of Things

·
Other emerging IT technology and industry areas

4. Good English skills, communication skills, and willingness to work with a global team. Skill in other languages is a plus.

5. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.

3.产品：DDR

地点：漕河泾

Verification Engineer

Qualifications
Master degree in EE/CS/ME.

Minimum of five  years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methodology.

Candidate should be familiar with industry standard ASIC design and verification tools and flow.

Good knowledge DDR protocol and computer system architecture would be an added advantage.

Good knowledge of Perl and shell programming would be an added advantage.

Responsibilities:
-Understanding the expected functionality of designs.
-Developing testing and regression plans.
-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.

Requirements:
Experience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
-Scripting and automation skills (tcl, perl, makefile etc) a plus.

-Knowledge of DDR protocol a plus.
-Independent and self-managing.

有意者可咨询：chloe-zhang@kthr.com；微信：13916933764；