加州洛杉矶关于45nm的高速ＡＤＣ论文

fenglingke · 发表于 2012-6-27 10:49:03

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In this thesis, a SoC (system on chip) solution is proposed for the IF (intermediate frequency) band signal processing and transmission of a radiometer system. This highly integrated and low-power solution is designed for systems where low ADC resolution (< 2-bit) is needed but high-speed data transmission (> 10Gbps) and low-power operation (< 10mW/channel) is strongly desired.
The presented solution includes an array of 2-bit ADCs with duty cycle controlled AGC (automatic gain control) function and a low-power 32:1 serializer. AGC function isincluded in the front end in order to cope with the wide range of input power (-10dBm ~ -20dBm). The AGC loop is controlled by digitized output duty cycle with an error of 2%. A current steering 5-level tree architecture serializer is designed to achieve a high serializing factor and low-power operation.
The circuit is designed using a 45nm SOI CMOS technology. It is capable of digitizing the IF signals using a power of 5.4mW/channel and transmitting the signals at 32Gbps. The serializer has an output reflection (S22) of less than -10dB from DC to 32GHz with 400mV differential output swing. The serializer consumes less than 50mW of power (3.2mW/channel), and the AGC loop consumes 2.2mW/channel.

TABLE OF CONTENTS
1 Introduction ………………………………………………………………… 1
1.1 Research Motivation …………………………………………………... 1
1.2 Organization of Thesis ………………………………………………… 3
2 Research Challenge…………………………………………………………. 5
2.1 AGC Loop Design Challenge…………………………………………….5
2.2 High-Speed Data Transmission Design Challenge……………….………12
3 Proposed Approach…………………………………………………….…..... 14
3.1 SOI 45nm CMOS Technology……………….…………………………..14
3.2 Overview of the Proposed System on Chip……….……………………. 16
3.3 Significance of Innovation ……………………………………………. 17
3.4 Potential Application …………………………………………………. 18
4 AGC Loop Design and Simulation…………………………………………. 19
4.1 VGA Design and Simulation ……….……….………………………… 19
4.2 2-bit ADC Design and Simulation……………………………………… 25
4.3 Duty Cycle Control Design and Simulation…………………………… 30
4.4 Charge Pump (OTA) Design and Simulation…………………………… 35
vi
4.5 AGC Loop Performance…………………….…………………………… 39
5 32:1 MUX Design and Simulation…………………………………………. 42
6 Conclusion…………………………...………………………………………. 46
References …………………………………………………………………….... 47

A 2bit 1Gsps ADC Array with 32 1 Serializer in 45nm CMOS SOI technology.zip (3.24 MB, 下载次数: 198 )