systemverilog problem in vcs

nano_dv

1.Error-[XMRE] cross-module reference resolution error.
Error found while trying to resolve cross-module reference token 'object'.Originating package '$unit'

---in this problem,i have included the file about the 'object',but the error still jump out.

2.Systemverilog keyword 'interface' is not expected to be used in this context.

---i had checked the interface definition .sv, i found no problem in the file.

littlelijia

1. Maybe it doesn't need 'object'.  I guess

sealna

遇到了和第二个类似的问题，但是不值得怎么解决

tiangua

1. 应该是比较弱智的问题，仔细看看，好好想想。光看报告也看不出什么来。
2. 是不是没有加参数 -sverilog

navie

第一个问题应该比较简单的
第二个，就比较奇怪了，你确定是在进行sv的编译么？

zzczx

什么版本？ 较早版本支持不好。换到2011后应该好点

sunsbank

怎么没人回答第一个问题，不管弱不弱智，得有人回答啊。

ztspac

疑问描述


While elaborating with VCS, the following error displays:

"Top Level Modules:
       top

Error-[XMRE] Cross-module reference resolution error
/proj/gsd/ids/13.1/ISE_DS/ISE/verilog/src/unisims/MMCM_ADV.v, 223
  Error found while trying to resolve cross-module reference.
  token 'glbl'.  Originating module 'MMCM_ADV'.
  Source info: assign GSR = glbl.GSR;"

解决方案


One reason for this issue is that the dangling top "glbl" is not provided on the VCS command line with the other top-level modules. If so, you can resolve the issue by using the command as follows:

vcs -top top -top vcs <other elab options>

ylz24385

1 交叉引用路径问题；一种可能是路径引用的错误；另一种可能是那个object是define的一个宏，在使用的时候没有加‘，应该是‘object。
2 定义interface的definition .sv应该没有问题，而是实例化该interface的construct有问题，比如有可能你是在program--endprogram里面实例化该interface等。

yanghuiqi

在环境中是不是需要virtual