Error: Failed to find 'PLL_LOCKG' in hierarchical name

eyeloveu · 发表于 2012-6-21 10:56:27

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今天在Modelsim仿真Xilinx设计的时候遇到了这样一个很奇怪的错误：

# Model Technology ModelSim SE vcom 6.5c Compiler 2009.08 Aug 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package vcomponents
# -- Compiling entity ii_clk_align
# -- Compiling architecture arch of ii_clk_align
# vsim -L work -L secureip -L simprims_ver -L uni9000_ver -L unimacro_ver -L unisims_ver -L unisim -L xilinxcorelib_ver -coverage -voptargs="+acc" -pli novas.dll -suppress 3486 -t 1ps -vopt work.glbl work.tb_top
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# ** Error: C:/Xilinx/12.3/ISE_DS/ISE/verilog/src/unisims/PLL_ADV.v(1108): Failed to find 'PLL_LOCKG' in hierarchical name.
# Optimization failed
# Error loading design

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网上搜了一下也没什么解决方法，glbl.v也看了，也看了脚本，都没问题。后来用debussy看了一下，发现glbl里果然没有'PLL_LOCKG‘，原来这个glbl的顶层和glbl.v的内容不一样，很多xilinx的IP里面自己也是带glbl模块的。于是原因找到了：我在脚本里把glbl.v是放在第一个compile的，所以后来的IP里自带的glbl把glbl.v给覆盖了，导致找不到'PLL_LOCKG‘。

解决方法：把glbl.v放到source file complie list的最后一个。

IP里的glbl

`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
wire GSR;
wire GTS;
wire PRLD;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule

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glbl.v

`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule

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JIANGXHUA · 发表于 2015-1-12 21:49:24

顺利解决，

~

[解决] Error: Failed to find 'PLL_LOCKG' in hierarchical name

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