VCS后仿$setuphold提示

loveheihei

本人在用icc导出的.v和pt导出的sdf文件反标后仿的时候总是遇到$setuphold提示的违例：                       

"smic13g_neg.v",18853: Timing violation in tb_pb_Cal.pb_cal_test.weight_3_reg_9_

    $setuphold(posedge CK:5348, posedge RN:5303, limits: (176,-37) );

"smic13g_neg.v",18781: Timing violation in tb_pb_Cal.pb_cal_test.weight_3_reg_11_

    $setuphold(posedge CK:5362, posedge RN:5302, limits: (234,-52) );

"smic13g_neg.v",18781: Timing violation in tb_pb_Cal.pb_cal_test.weight_tmp_3_reg_11_

    $setuphold(posedge CK:5362, posedge RN:5302, limits: (234,-52) );

"smic13g_neg.v",18853: Timing violation in tb_pb_Cal.pb_cal_test.weight_tmp_3_reg_19_

    $setuphold(posedge CK:5362, posedge RN:5302, limits: (173,-36) );

"smic13g_neg.v",18781: Timing violation in tb_pb_Cal.pb_cal_test.weight_3_reg_13_

    $setuphold(posedge CK:5362, posedge RN:5302, limits: (234,-52) );

"smic13g_neg.v",18781: Timing violation in tb_pb_Cal.pb_cal_test.weight_3_reg_19_

    $setuphold(posedge CK:5362, posedge RN:5302, limits: (234,-52) );

"smic13g_neg.v",18853: Timing violation in tb_pb_Cal.pb_cal_test.weight_3_reg_18_

    $setuphold(posedge CK:5363, posedge RN:5302, limits: (173,-36) );

"smic13g_neg.v",18781: Timing violation intb_pb_Cal.pb_cal_test.weight_tmp_3a_reg_14_

    $setuphold(posedge CK:5375, posedge RN:5304, limits: (231,-52) );

"smic13g_neg.v",18781: Timing violation intb_pb_Cal.pb_cal_test.weight_tmp_3a_reg_10_

    $setuphold(posedge CK:5375, posedge RN:5303, limits: (231,-52) );

"smic13g_neg.v",18781: Timing violation intb_pb_Cal.pb_cal_test.weight_tmp_3a_reg_12_

    $setuphold(posedge CK:5375, posedge RN:5304, limits: (231,-52) );

"smic13g_neg.v",18781: Timing violation intb_pb_Cal.pb_cal_test.weight_tmp_3a_reg_11_

    $setuphold(posedge CK:5375, posedge RN:5304, limits: (231,-52) );

这个提示到底是setup 违例还是hold time违例呢，那个limits总是看不懂

这个case的icc和pt什马的都过了，但是一直有这个错误提示，vcs后仿总是失败。。。求大神指导阿。。。

loveheihei

木人瓦，我看了下库里面的定义有那个一段儿：
`timescale 1ns/1ps
`celldefine
module DFFRX2 (Q, QN, D, CK, RN);
output Q, QN;
input  D, CK, RN;
reg NOTIFIER;
supply1 xSN;

  buf   XX0 (xRN, RN);
supply1 dSN;
wire dD;
wire dCK;
wire dRN;
  buf     IC (clk, dCK);
  udp_dff I0 (n0, dD, clk, dRN, dSN, NOTIFIER);
  and     I4 (flag, dRN, dSN);
  buf     I1 (Q, n0);
  not     I2 (QN, n0);

  specify
    specparam
    tplh$RN$Q  = 1.0,
    tphl$RN$Q  = 1.0,
    tplh$RN$QN  = 1.0,
    tphl$RN$QN  = 1.0,
    tplh$CK$Q        = 1.0,
    tphl$CK$Q        = 1.0,
    tplh$CK$QN        = 1.0,
    tphl$CK$QN        = 1.0,
    tsetup$D$CK        = 1.0,
    thold$D$CK        = 0.5,
    tsetup$RN$CK    = 1.0,
    thold$RN$CK    = 0.5,
    tminpwl$RN     = 1.0,
    tminpwl$CK    = 1.0,
    tminpwh$CK    = 1.0,
    tperiod$CK    = 1.0;


    if (flag)
      (posedge CK *> (Q +: D)) = (tplh$CK$Q,    tphl$CK$Q);
    if (flag)
      (posedge CK *> (QN -: D)) = (tplh$CK$QN,   tphl$CK$QN);
    $setuphold(posedge CK &&& (flag == 1), posedge D, tsetup$D$CK, thold$D$CK, NOTIFIER, , ,dCK,dD);
    $setuphold(posedge CK &&& (flag == 1), negedge D, tsetup$D$CK, thold$D$CK, NOTIFIER, , ,dCK,dD);
      (negedge RN *> (Q +: 1'b0)) = (tphl$RN$Q);
      (negedge RN *> (QN -: 1'b0)) = (tplh$RN$QN);
    $setuphold(posedge CK, posedge RN, tsetup$RN$CK, thold$RN$CK, NOTIFIER, , ,dCK,dRN);
    $width(negedge RN, tminpwl$RN, 0, NOTIFIER);
    $width(negedge CK &&& (flag == 1), tminpwl$CK, 0, NOTIFIER);
    $width(posedge CK &&& (flag == 1), tminpwh$CK, 0, NOTIFIER);
    $period(posedge CK &&& (flag == 1), tperiod$CK, NOTIFIER);

   endspecify
endmodule // DFFRX2
`endcelldefine

这个库里面的关于CLK和RN的$setuphold的notifier和一般的setuphold time定义貌似不太一样，我改了下testbench就搞定了,貌似是RN保持的时间不足

bigbird

以第一行为例：
"smic13g_neg.v",18853: Timing violation in tb_pb_Cal.pb_cal_test.weight_3_reg_9_
    $setuphold(posedge CK:5348, posedge RN:5303, limits: (176,-37) );
5348-5303=47<176，setup也就是recovery满足，
5303-5348=-47，绝对值超过了-37，因此hold不满足。
原因：要么pt没有分析到，要么电路上这个地方是false path。

Tonyhai

学习了，多谢

yangfugeng11

学习，路过。

s19812500

这个解释怎么感觉有点和看文档的不同呢？

kekeguda

回复 3# bigbird


   这个可以看到data_event（RN）是在reference_event（CK）的前面，这个应该是建立时间吧，建立时间只有47<最小建立时间176，因此不满足建立时间的条件。这里跟保持时间没关系吧
下面的是$setuphold的定义，引自verilog2001的标准：
$setuphold ( reference_event , data_event , timing_check_limit ,  timing_check_limit
[ , [ notify_reg ] [ , [ stamptime_condition ] [ , [ checktime_condition ]
[ , [ delayed_reference ] [ , [ delayed_data ] ] ] ] ] ] )

harejavahill

3楼正解

shengjun066

楼主，看了这个标准单元的定义：
其中CK,D,RN 端口 ，和dD,dCK,xRN 怎么连接的，没有看到相关语句。一般不是wire类型的需要配合assign语句赋值么？
难道是跟这句有关：
$setuphold(posedge CK &&& (flag == 1), negedge D, tsetup$D$CK, thold$D$CK, NOTIFIER, , ,dCK,dD);
可是看语句解释，没有看到相关解释？

diyangguang

3楼正解