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大家好。为了提高RAM读取速度，用21个小RAM组成了一个大RAM，可以在一个周期内读取不同小RAM来实现读取多个数据。读端口有8个，写端口有两个。控制方法为每个小RAM单独判断这些读写信号是否有效，是否与本RAM相关。若读写是自己，该读的时候读，该写的时候写，读写同时时先缓冲写数据，读完毕后写入。因为都是独立判断读写，所以每一个小RAM都用到了这些读写信号，而且在内部判断是否与自己相关时也会用到。综合完毕后，这个模块占的资源很大，是不是就是因为读写信号扇出太大造成的吗？如果把这些读写信号分别保存到七组寄存器中，会不会解决这个问题呢？
reg [4:0] address_a1;
reg [16:0] data_a1;
reg wren_a1;
wire [16:0] q_a1;
reg [4:0] address_b1;
reg [16:0] data_b1;
reg wren_b1;
wire [16:0] q_b1;
Line line1(
clk,
reset_n,
address_a1,
address_b1,
data_a1,
data_b1,
wren_a1,
wren_b1,
q_a1,
q_b1);
reg [4:0] addr_a1;
reg [16:0] unsave_a1;
reg ij_a1;
reg [4:0] addr_b1;
reg [16:0] unsave_b1;
reg ij_b1;
wire read_line1_1,read_line1_2;
assign read_line1_1=read_en_1&&(address1_a1[9:5]==0||address1_d1[9:5]==0);
assign read_line1_2=read_en_1&&(address2_a1[9:5]==0||address2_d1[9:5]==0);
always @(posedge clk or negedge reset_n)
if(!reset_n)
begin
ij_a1<=0;
addr_a1<=0;
unsave_a1<=0;
address_a1<=0;
data_a1<=0;
wren_a1<=0;
ij_b1<=0;
addr_b1<=0;
unsave_b1<=0;
address_b1<=0;
data_b1<=0;
wren_b1<=0;
end
else if(read_line1_1 || read_line1_2 || (iwrite_en_a && iaddress_a[9:5]==0) || (iwrite_en_b && iaddress_b[9:5]==0))
begin
case({read_line1_1|read_line1_2,(iwrite_en_a && iaddress_a[9:5]==0) || (iwrite_en_b && iaddress_b[9:5]==0)})
2'b01:
begin
if(iwrite_en_a && iaddress_a[9:5]==0)
begin
address_a1<=iaddress_a[4:0];
data_a1<=idata_a;
wren_a1<=1;
end
if(iwrite_en_b && iaddress_b[9:5]==0)
begin
address_b1<=iaddress_b[4:0];
data_b1<=idata_b;
wren_b1<=1;
end
end
2'b10:
begin
if(address1_a1[9:5]==0)
begin
address_a1<=address1_a1[4:0];
wren_a1<=0;
address_b1<=address1_b1[4:0];
wren_b1<=0;
end
else if(address1_d1[9:5]==0)
begin
address_a1<=address1_c1[4:0];
wren_a1<=0;
address_b1<=address1_d1[4:0];
wren_b1<=0;
end
else if(address2_a1[9:5]==0)
begin
address_a1<=address2_a1[4:0];
wren_a1<=0;
address_b1<=address2_b1[4:0];
wren_b1<=0;
end
else if(address2_d1[9:5]==0)
begin
address_a1<=address2_c1[4:0];
wren_a1<=0;
address_b1<=address2_d1[4:0];
wren_b1<=0;
end
end
2'b11:
begin
if(address1_a1[9:5]==0)
begin
address_a1<=address1_a1[4:0];
wren_a1<=0;
address_b1<=address1_b1[4:0];
wren_b1<=0;
end
else if(address1_d1[9:5]==0)
begin
address_a1<=address1_c1[4:0];
wren_a1<=0;
address_b1<=address1_d1[4:0];
wren_b1<=0;
end
else if(address2_a1[9:5]==0)
begin
address_a1<=address2_a1[4:0];
wren_a1<=0;
address_b1<=address2_b1[4:0];
wren_b1<=0;
end
else if(address2_d1[9:5]==0)
begin
address_a1<=address2_c1[4:0];
wren_a1<=0;
address_b1<=address2_d1[4:0];
wren_b1<=0;
end
if(iwrite_en_a && iaddress_a[9:5]==0)
begin
addr_a1<=iaddress_a[4:0];
unsave_a1<=idata_a;
ij_a1<=ij_a1+1;
end
if(iwrite_en_b && iaddress_b[9:5]==0)
begin
addr_b1<=iaddress_b[4:0];
unsave_b1<=idata_b;
ij_b1<=ij_a1+1;
end
end
default:;
endcase
end
else
begin
if(ij_a1>0)
begin
address_a1<=addr_a1;
data_a1<=unsave_a1;
wren_a1<=1;
ij_a1<=ij_a1-1;
end
else
begin
address_a1<=0;
data_a1<=0;
wren_a1<=0;
end
if(ij_b1>0)
begin
address_b1<=addr_b1;
data_b1<=unsave_b1;
wren_b1<=1;
ij_b1<=ij_b1-1;
end
else
begin
address_b1<=0;
data_b1<=0;
wren_b1<=0;
end
end
每一个RAM的控制都类似，只是判断地址的前半部分的时候不一样。功能上没有问题，但综合时占的资源太多了。我也想不到为什么会占那么多，有什么好的方法来优化呢？谢谢各位了。 |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2012-6-18 18:57:32
楼主