|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
本帖最后由 退休的红领巾 于 2012-5-4 16:27 编辑
Three-Stage Large Capacitive Load Amplifier withDamping-Factor-Control Frequency Compensation
Abstract—A novel damping-factor-control frequency compensation(DFCFC) technique is presented in this paper with detailedtheoretical analysis. This compensation technique improves frequencyresponse, transient response, and power supply rejectionfor amplifiers, especially when driving large capacitive loads.Moreover, the required compensation capacitors are small andcan be easily integrated in commercial CMOS process.
Amplifiers using DFCFC and nested Miller compensation(NMC) driving two capacitive loads, 100 and 1000 pF, were
fabricated using a 0.8-m CMOS process with Vtn = 0.72 V andVtp = 0.75 V. For the DFCFC amplifier driving a 1000-pF load,a 1-MHz gain-bandwidth product, 51 phase margin, 0.33-V/sslew rate, 3.54-s settling time, and 426-W power consumptionare obtained with integrated compensation capacitors. Comparedto the NMC amplifier, the frequency and transient responses ofthe DFCFC amplifier are improved by one order of magnitudewith insignificant increase on the power consumption.Index Terms—Damping factor, frequency compensation, largecapacitive load, multistage amplifier.
香港大學Philip K. T. Mok教授的paper.pdf
(266.69 KB, 下载次数: 176 )
|
|