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大家好,我是NVIDIA Physical Design Methodology team的负责人,近期部门扩张,新增了多个社招名额,希望对此方向感兴趣的朋友来信交流
简单描述如下:
Physical Design Methodology Engineer
要求:
- 后端或者EDA PV/AE/AC/RD经验2年以上
- 熟悉后端流程,理解制造工艺
- 对写脚本编程感兴趣,有较多的Tcl/Perl编程经验
职责:
- 负责20/28nm基于ICC/Talus的后端流程的开发
- 提升流程自动化程度
- 为项目提供支持
- 评估EDA工具
更为详细的JD请看后面的英文内容。从工作2年到10年的都可以,具体待遇看个人情况。
目前美国总部要逐渐把后端流程放到海外做了,所以机遇还是不错的。我们不是简单的测试和支持,已经有完全独立负责的重要模块了。
有任何问题,欢迎来信交流 madi@nvidia.com
JD:
SR. PHYSICAL DESIGN METHODOLOGY ENGINEER
RESPONSIBILITIES:
- Responsible for the development of thephysical design methodologies and flow automation for large and high speedsemicustom chips using deep submicron processes. This includes evaluating andhelping improve third party tools, developing internal tools and solutions, andsupporting the physical design implementation team.
MINIMUM REQUIREMENTS:
- BSEE or BSCS
- 3+ years of experience in large VLSI physicaldesign implementation and automation and methodology.
- Strong experience in programming of one of thefollowing area: C/C++, Perl, Python.
- Prior experience in timing closure, CTS, powerdistribution and analysis, power efficiency, RC extraction and correlation,xtalk analysis, signal EM,
place and route, DRC/LVSand tapeout issues.
- Working knowledge of deep sub-micronissues.
- Should be a power user of P&R and timinganalysis CAD tools from Magma (Blast, Talus), Synopsys(ICC/DC/PT/STAR-RC/Astro/PC), Cadence (SOCE), Mentor Graphics(Pinnacle/Olympus) or Atoptech.
- Proficiency using Perl, TCL, Makescripting.
- Knowledge/Proficiency of C/C++ or any othersoftware language is a plus.
- Experience at 40nm and 28nm is a plus.
- Circuit level comprehension of time criticalpaths and Spice experience are a plus.
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