*info: there are 2 max_cap violations in the design.
*info: 1 violation is real.
*info: 1 violation may not be fixable:
*info: 1 violation on multiple fanin net (remark M).
*info: there are 6 max fanout load violations in the design.
*info: 5 violations are real.
*info: 1 violation may not be fixable:
*info: 1 violation on clock net (remark C).
请问这种violations会不会影响后面的布局布线、还有DRC/LVS等等的操作?能否继续操作下去,如何进行校正呢?
小弟经过时序优化之后,发现上述violation消失了,但仍然还有些violation优化不了,例如报告中还会有: Net / InstPin MaxFanLoad FanLoad FanLoadSlk CellPort Remark
#
clk__L8_N0
clk__L8_I0/Y 15.000 38.000 -23.000 BUFX12/Y C
*info: there is 1 max fanout load violation in the design.
*info: 0 violation is real.
*info: 1 violation may not be fixable:
*info: 1 violation on clock net (remark C).
请问这个unable fix violation怎么修正呢?谢谢