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发表于 2012-10-28 22:17:05
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QRC是sign-off工具
采用Cadence Encounter Flow的design都采用QRC为sign-off工具,请看官网新闻:
TSMC Selects Cadence Virtuoso and Encounter Platforms for its 20nm Design Infrastructure, Spanning Custom/Analog, Digital and Mixed-Signal Design Cadence Design, Verification, Implementation and Signoff Technology
SAN JOSE, Calif., 16 Oct 2012
http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=101612_tsmc
文中说:
For signoff, the Cadence Encounter Timing System offers advanced waveform modeling and multi-valued SPEF for double-patterning RC extraction. Cadence QRC Extraction delivers a DPT-aware corners extraction technology that supports both LEF/DEF and GDSII flows. The Cadence Physical Verification System offers support of 20-nanometer double-patterning and incremental DRC correction, and TSMC rule decks are now available for the Physical Verification System. Encounter Power System provides accurate, basic and complex topology-dependent EM rules, and Litho Physical Analyzer and Litho Electrical Analyzer have been updated with 20-nanometer models for hotspot analysis and repair.
TSMC 20nm 认可,元芳,你怎么看? |
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