参数的提取

XIDIANCAD2 · 发表于 2012-1-31 18:01:32

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在encounter里可以用QRC提取参数吗？具体怎么弄？我是直接在encounter里的timing菜单下的RC extraction里提取spef文件的。不知道什么是QRC参数提取。

icfbicfb · 发表于 2012-1-31 22:50:17

命令是runQRC
,
也可以导出def，然后run 单独的qrc 来做

XIDIANCAD2 · 发表于 2012-2-1 08:28:49

回复 2# icfbicfb

谢谢，直接在encounter里的timing菜单下的RC extraction里提取spef文件是不是不太精确？一般是用QRC参数对吧？

XIDIANCAD2 · 发表于 2012-2-1 08:32:15

回复 2# icfbicfb

版主，帮我看下这个问题：
版图生成后用PT做STA，用于PT的tcl如下：
set search_path "."
set link_path "*fs90a_c_generic_core_ss2p25v125c.db fs90a_c_generic_core_tt2p5v25c.db coef_mem_ss.db coef_ram_wc.db data_ram_wc.db"
read_verilog /...eua2308_dap_ram_soc_12_01_30.v
current_design eua2308_dap_ram
link_design eua2308_dap_ram
set_min_library fs90a_c_generic_core_ss2p25v125c.db -min_version fs90a_c_generic_core_ff2p75vm40c.db
set_min_library data_ram_wc.db -min_version data_ram_bc.db
set_min_library coef_ram_wc.db -min_version coef_ram_bc.db
set_min_library coef_mem_ss.db -min_version coef_mem_ff.db
set_driving_cell -lib -cell DFFN -pin Q -no_design_rule [all_inputs] -library fs90a_c_generic_core_tt2p5v25c
set_wire_load_model -name enG50K -lib fs90a_c_generic_core_tt2p5v25c
set_wire_load_mode enclosed
set_operation_conditions -analysis_type on_chip_variation -min BBCOM -min fs90a_c_generic_core_ff2p75vm40c.db -max WWCOM -fs90a_c_generic_core_ss2p25v125c.db
create_clock_period 38 -waveform{0 19} PLL_CLK
set_load 5e-1[all_outputs]
set_drive 0 {PLL_CLK}
set_dont_touch_network {PLL_CLK}
set_propagated_clock [get_ports PLL_CLK]
set_clock_uncertainty -setup 0.3 [get_clocks PLL_CLK]
set_clock_uncertainty -hold 0.2 [get_clocks PLL_CLK]
set_input_delay 2 [remove_from_collection [all_inputs] [get_ports PLL_CLK]] -clock PLL_CLK
set_output_delay 1 [all_outputs] -clock PLL_CLK

然后执行read_parasticts /...eua2308_dap_ram12_01_30.spef语句结果出现以下
warning:unconnected hierarchy pin'eua2308_dap_u/eua2308_dap_control_u/no_cycle'is missing in the RC annotation for net
'eua2308_dap_u/eua2308_dap_control_u/no.cycle'
warning:unconnected hierarchy pin'eua2308_dap_u/eua2308_dap_control_u/sck_pos_edge'is missing in the RC annotation for net
'eua2308_dap_u/eua2308_dap_control_u/sck_pos_edge'

net type                      total          lumped       RC pi             RC network             not annotated
internal nets                21933          0                0                      21629                      0
      -driverless nets                      0                0                      0                            231
   -loadless nets                         0                0                      0                               73

   boundary/port nets 180          0                0                      180                            0
   -driverless nets                         0                0                         0                               0
   -loadless nets                            0                0                         0                               0

                                    22113    0                0                         21809                            304

再运行report_timing -delay min
      report_timing -delay max
后出现warning
warning:some timing arcs have been disaabled for breaking timing loops or because of constant propagation
下面的相类似的warning很多，我只列了一个
warning:failed to compute c_effective for the timing arc(data_ram_wc/data_ram)data_ram_u/ck-->DO2(max_falling retain_rising)because the library data indicates a non_positive drive resistance

这些warning一定要排除吗？是什么原因引起的？怎么解决？麻烦帮我分析下。非常感谢

XIDIANCAD2 · 发表于 2012-2-1 09:41:04

回复 2# icfbicfb

我直接在encounter中输入命令：runQRC 结果出现以下信息：
writing DEF file '.qx.def'
unitpermicron=1000,dbgmicrunperPBU=0.001000
unitperDBU=1.0000
DEF file'.qx.def' is written
'qrc'failed to finish successfully'
error:qrc failed
不知道怎么回事。