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module OutMod(
rst,
clk,
clkp,
clkv,
clkh,
AorB,
Din,
switch,
Dclk,
Dout
);
input rst;
input clk;
input clkp;
input clkv;
input clkh;
input switch;
input AorB;
input[7:0] Din;
output Dclk;
output[8:0] Dout;
reg[8:0] Dout;
reg[2:0] OutOrder;
reg copy_v;
reg copy_h;
reg hen;
reg Yen;
reg frame_logo;
reg time_en;
reg[1:0] outByte;
reg AnalysisEnd;
reg[8:0] y_Num;
reg[9:0] x_Num;
reg Byte_add;
//reg[8:0] yBuf;
reg[9:0] xBuf;
reg[9:0] xBufA;
reg[9:0] xBufB;
reg[9:0] xBufC;
//reg[9:0] xBufD;
reg[9:0] y_out;
reg[9:0] x_out;
//reg[7:0] max_Dbuf;
wire Add_en;
wire Dclk;
wire en_v;
wire en_h;
parameter YUYV = 1'b0;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100 ;
parameter SS0 = 2'b00, SS1 = 2'b01, SS2 = 2'b10, SS3 = 2'b11;
assign Add_en = !Byte_add & y_Num[5];
assign en_v = !copy_v & clkv;
assign en_h = !copy_h & clkh;
assign Dclk = Byte_add;
always @(posedge clkp) begin
if(rst == 1'b0) begin
OutOrder <= 1'b0; //
frame_logo <= 1'b0;
end
else begin
copy_v <= clkv;
if(en_v == 1'b1) begin
frame_logo <= !frame_logo;
if((OutOrder[2] == 1'b1)||(switch == 1'b0))
OutOrder <= 1'b0;
else
OutOrder <= OutOrder + 1'b1;
end
end
end
always @(posedge clkp) begin
if(clkv == 1'b0) begin
y_Num <= 1'b0;
end
else begin
copy_h <= clkh;
if(en_h == 1'b1)
y_Num <= y_Num + 1'b1;
end
if(clkh == 1'b0) begin
x_Num <= 1'b0;
Yen <= 1'b0;
end
else begin
Yen <= !Yen;
if(Yen == YUYV)
x_Num <= x_Num + 1'b1;
end
end
reg h_begin;
reg[2:0] inNum;
always @(posedge clk) begin
if(clkv == 1'b0) begin
inNum <= 1'b0;
end
else begin
if(clkh == 1'b0) begin
h_begin <= 1'b0;
if(h_begin == 1'b1)
inNum <= inNum + !inNum[2];
end
else if(max == 1'b1) begin
yBuf <= y_Num;
h_begin <= 1'b1;
end
end
end
always @(posedge clk) begin
if({clkh,h_begin} == 2'b01) begin
xBufA <= xBuf;
xBufB <= xBufA;
xBufC <= xBufB;
//xBufD <= xBufC;
end
if(AnalysisEnd == 1'b0) begin
if(OutOrder[0] == 1'b1) begin
if({max,h_begin} == 2'b10) // get coordinates of the left boundary, Boundary scan of 4 points
xBuf <= x_Num;
end
else begin
if(max == 1'b1) // get coordinates of the right boundary,Boundary scan of 4 points
xBuf <= x_Num;
end
end
end
wire[9:0] summand;
wire[9:0] Sum;
assign summand = (OutOrder[1] == 1'b1) xBufC : xBufA; // 1, 4 ; 2, 3;
assign Sum = summand + 2'b10; // Scanning the slope of the corner : 45°
always @(posedge clkp) begin
if(clkv == 1'b0) begin
AnalysisEnd <= 1'b0;
if(AnalysisEnd != 1'b0) begin
x_out <= xBufC;
y_out <= {frame_logo,y_Num};
end
end
else if({AnalysisEnd,inNum[2]} == 2'b01) begin
case(OutOrder)
S0 :
S1 : if(xBufC <= Sum)
AnalysisEnd <= 1'b1;
S2 : if(xBufA <= Sum)
AnalysisEnd <= 1'b1;
S3 : if(xBufA >= Sum)
AnalysisEnd <= 1'b1;
S4 : if(xBufC >= Sum)
AnalysisEnd <= 1'b1;
default: ;
endcase
end
end
always @(posedge clkp) begin
if(clkv == 1'b0) begin
outByte <= 1'b0;
end
else begin
Byte_add <= y_Num[5];
if(Add_en == 1'b1) begin
if(outByte == 2'b11)
time_en <= 1'b0;
else begin
time_en <= 1'b1;
outByte <= outByte + 1'b1;
end
end
end
end
always @(posedge clkp) begin
if(Add_en == 1'b1) begin
case(outByte)
SS0 : if(OutOrder == S1)
Dout <= {y_out[9],8'hff};
else
Dout <= {y_out[9],6'b0, x_out[9:8]};
SS1 : if(OutOrder == S1)
Dout <= {y_out[9],8'hff};
else
Dout <= {y_out[9],x_out[7:0]};
SS2 : Dout <= {y_out[9],7'b0, y_out[8]};
SS3 : Dout <= {y_out[9],y_out[7:0]};
default : ;
endcase
end
end
endmodule |
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发表于 2012-1-18 13:52:52
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