why 's the ddr_hp_controller signal local_init_done always "0"

gerry1812

Hi,

The HPCII native interface documentation is very poor, so I try to simulate my design to verify read and write operations.

I use Quartus 10.1 sp1 / modelsim 6.6c
HPC II : - PSC A2S56D40CTP-G5 DDR (cycIII starter kit DDR), burst x4
- full calibration & generate simulation model options

I made a testbench with my ddr_driver (which drive local signals), ddr IP and quartus generated memory model.
The internal PLL works (phy_clk, mem_clk, aux_full_rate_clk... are generated) but the DDR IP seems to fail its initialization/calibration :
- local_init_done, local_ready, ctl_cal_fail, ctl_cal_success... are all at '0'.

Is it possible to simulate ddr calibration ? How can I pass this step and get local_ready asserted ?

Thanks.

xiaohonging

check your tb first

njinji

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