pipeline ADC 1.5bit/stage 数字校准最经典的算法

joezl82 · 发表于 2011-12-21 10:39:28

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做pipeline ADC必看，Stephen H. Lewis 1992年的paper
A 10-b 20-Msample/s Analog-to-Digital Converter

Abstract—This paper describes a 10-b 20-Msample/s analog-
to-digital converter fabricated in a 0.9-pm CMOS technology.
The converter uses a pipelined nine-stage architecture with fully
differential analog circuits and achieves a signal-to-noise-and-
distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal
input at 5 MHz. It occupies 8.7 mmz and dissipates 240 mW.

A 10 b 20 Msample s analog to digital converter.pdf (1.22 MB, 下载次数: 1576 )