1. The first part should be only used by single bit retiming. Mostly used by sync Asynchronous signal. Never use it on Data Bus directly.
2. That the edge detection. It is the normal way to do it. If you use @(posedge xxx), the synthesis tool sometime would this that is another generated clock. Most time that is not what we want. You can try to synthesis it and check what's the difference between these two style.