都是PAD 端口上的 ,一共有五类:
1 NO drive assertion
2 NO input delay or arrival time assertion
3 Unconstrained signal arriving at end point
4 Missing specific input delay or arrival time assertion for signal clk2 lead
5 Master clock edge does not reach the target for generated clock clk1
第5个是导致后面PT的一个从端口上的时钟找不到。