(ieee1998)A 1.5V, 10-bit, 14MS/s CMOS Pipeline Analog-to-Digital Converter

semico_ljj

A 1.5V, 10-bit, 14MS/s CMOS Pipeline Analog-to-Digital Converter

by
Andrew M. Abo and Paul R. Gray
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley
Berkeley, CA, USA

Abstract
A1.5V, 10-bit, 14.3MS/s pipeline analog-to-digital converter
was implemented in a 0.6mCMOS technology. Emphasiswas
placed on observing device reliability constraints at low voltage.
MOS switches were implemented without low-threshold
devices by using a bootstrapping technique that does not subject
the devices to large terminal voltages. The converter achieved
a peak SNDR of 58.5 dB, maximum DNL of 0.51 LSB, maximum
INL of 0.66 LSB and a power consumption of 36 mW.

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回复 1# semico_ljj
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A 1.5V, 10-bit, 14MS/s CMOS Pipeline Analog-to-Digital Converter

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