Blue Pearl Suite自动生成时序约束

bluepearl

Why Create Timing Constraints™?
Designs are increasingly becoming larger and more complex. They often have embedded processors, intellectual property, other pre-existing modules and multiple clocks. As these designs push the limits of area, power, and performance, the fastest timing routes quickly become congested and it gets more difficult to optimize for performance.
Timing constraints, which include clock rates, I/O delays, and timing exceptions, direct the synthesis and place & route tools to achieve the necessary timing targets to meet performance requirements and close timing quickly.
It is very difficult to manually identify timing exceptions. With billions of paths in a single design, these timing exceptions are often incomplete or inaccurate, ** timing closure the single most time-consuming task, next to verification.
Create Timing Constraints™
Identifies false and multi-cycle paths from RTL descriptions and writes SDC timing constraints for implementation as well as SVA or PSL assertions for verification. Create reduces iterations in the flow to achieve timing closure faster, minimizing design risk.
The Blue Pearl Visual Verification environment consists of four tools that allow you to evaluate, verify, understand and take full advantage of the constraints and assertions generated by the Blue Pearl Software Suite. The False & Multi-cycle Path Audit Trail Viewer and the Assertion Audit Trail Viewer are associated with the Create product.
Both tools consist of three dockable sub-windows within a main schematic window that show a color-coded view of only the selected path. The first sub-window in the Assertion Audit Trail Viewer is a list of assertions. Selecting an assertion from this list opens a filterable list of false paths associated with that assertion. The first sub-window in the False & Multi-cycle Path Audit Trail Viewer (see below) is a filterable list of false and multi-cycle paths from the current design.
The solution is to automatically generate a set of compact, efficient, effective constraints using a conservative approach, irrespective of circuit, so that the constraints are valid. The right tool should work at both the RTL and gate level. Why? Because verification is faster and more accurate at RTL.Common causes of timing closure delays:

• Designing with an incomplete set of constraints
• Accidentally introducing errors in timing exceptions
• Multiple design iterations
• Over-constrained or under-constrained designs
• Timing failure
• Difficulty identifying very complex multi-cycle paths

The Blue Pearl Software Suite is built with industry-leading symbolic simulation technology to automatically generate the timing exceptions from RTL code. With Blue Pearl, designers can accomplish in just a few short hours what might normally take designers many weeks of work.Features & Benefits:

• Fast FSM and control behavior analysis
• Sequential analysis of false and multi-cycle paths
• Generates timing exception constraints for:
  • - Capitalize signals in signals crossing
    clock domains
  • - Resets and constrained signals
  • - Configuration registers
  • - Functional false paths (FPs)
  • - Multicycle paths (MCPs)
  • - Block level MCPs where cyclic signalsemanate from block ports
• Compares constraints in different SDC files
• Migrates block constraints to top-level constraints
• Supports .lib descriptions for IP blocks
• Generates PSL/SVA assertions for simulation/ formal verification

http://www.bluepearlsoftware.com/create/

                               
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creese

软件是好软件，但是到哪里能找到可使用版呢？

liujian_2009

这个软件是在linux下还是在windows下运行的？

tian2021

回复 3# liujian_2009


支持windows  和linux

raghuswill

Very helpful for impact power constraints