VLSI Physical Design_From Graph Partitioning to Timing Closure

ahhfdxq · 发表于 2011-11-3 21:23:30

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很好的VLSI设计方面的资料，仅供参考。
VLSI Physical Design_From Graph Partitioning to Timing Closure
VLSI physical design of integrated circuits underwent explosive development in the
1980s and 1990s. Many basic techniques were suggested by researchers and implemented
in commercial tools, but only described in brief conference publications
geared for experts in the field. In the 2000s, academic and industry researchers focused
on comparative evaluation of basic techniques, their extension to large-scale
optimization, and the assembly of point optimizations into multi-objective design
flows. Our book covers these aspects of physical design in a consistent way, starting
with basic concepts in Chapter 1 and gradually increasing the depth to reach advanced
concepts, such as physical synthesis. Readers seeking additional details, will
find a number of references discussed in each chapter, including specialized monographs
and recent conference publications.
Chapter 2 covers netlist partitioning. It first discusses typical problem formulations
and proceeds to classic algorithms for balanced graph and hypergraph partitioning.
The last section covers an important application – system partitioning among multiple
FPGAs, used in the context of high-speed emulation in functional validation.
Chapter 3 is dedicated to chip planning, which includes floorplanning, powerground
planning and I/O assignment. A broad range of topics and techniques are
covered, ranging from graph-theoretical aspects of block-packing to optimization by
simulated annealing and package-aware I/O planning.
Chapter 4 addresses VLSI placement and covers a number of practical problem
formulations. It distinguishes between global and detailed placement, and first covers
several algorithmic frameworks traditionally used for global placement. Detailed
placement algorithms are covered in a separate section. Current state of the art
in placement is reviewed, with suggestions to readers who might want to implement
their own software tools for large-scale placement.
Chapters 5 and 6 discuss global and detailed routing, which have received significant
attention in research literature due to their interaction with manufacturability
and chip-yield optimizations. Topics covered include representing layout with graph
models and performing routing, for single and multiple nets, in these models. Stateof-
the-art global routers are discussed, as well as yield optimizations performed in
detailed routing to address specific types of manufacturing faults.
Chapter 7 deals with several specialized types of routing which do not conform with
the global-detailed paradigm followed by Chapters 5 and 6. These include non-
Manhattan area routing, commonly used in PCBs, and clock-tree routing required
for every synchronous digital circuit. In addition to algorithmic aspects, we explore
the impact of process variability on clock-tree routing and means of decreasing this
impact.

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