【AMD上海】招聘multimedia方面的设计以及验证工程师

RecruiterAMD

1. ASIC Design Engineer - Display

DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Responsible for display IP development and maintenance
- Responsible for IP level synthesis/formal check
- Work with verification engineer on IP level validation
- Work with front-end integration team and physical design team on timing closure
- Communication with driver team to build driver

PREFERRED EXPERIENCE:
- Bachelor with 5+ yeas and Master with 3+ in Electrical or Computer Engineering.
- Strong RTL coding and familiar with front-end design flow
- Experience on synthesis, timing analysis and formal verification.
- Experience of display specific-interconnection protocols (DisplayPort, LVDS, VGA,HDCP, DVI, HDMI etc) is a plus.
- Design for verification (assertion based design strategies, code coverage, functional
coverage, test plan etc.)
- Good communication skills and fluent English.
- Strong responsibilities and team spirit.

2. Sr. ASIC Design Engineer

Job Responsibilities:
- Participate IP and SoC level design and verification work
- Simulate and debug the codes in coding stage.
- Write ASIC specific part of test plan. Co-work with FPGA/verification engineers to prove functional correctness from block level to SoC level
- Support Firmware bring-up and debugging
- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.

Preferred Experience:
- Major in EE & CS
- Be proficient in C/C++/SystemVerilog experience
- Should be familiar with shell/perl/tcl programming in linux OS.
- Will be a plus if having Verilog coding, debugging and modeling experience
- Will be a plus if having FPGA validation experience

3. MTS Design Verification Engineer - Display

DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Responsible for display IP development and maintenance
- Responsible for IP level synthesis/formal check
- Work with verification engineer on IP level validation
- Work with front-end integration team and physical design team on timing closure
- Communication with driver team to build driver

PREFERRED EXPERIENCE:
- Bachelor with 5+ yeas and Master with 3+ in Electrical or Computer Engineering.
- Strong RTL coding and familiar with front-end design flow
- Experience on synthesis, timing analysis and formal verification.
- Experience of display specific-interconnection protocols (DisplayPort, LVDS, VGA,HDCP, DVI, HDMI etc) is a plus.
- Design for verification (assertion based design strategies, code coverage, functional
coverage, test plan etc.)
- Good communication skills and fluent English.
- Strong responsibilities and team spirit.

4. Staff Firmware Engineer for Image Processor

Role and Chance:
1.Developing image processor related algorithms.
2.Work with driver team and AE team for bring-up support and customer support
3.Participate in chip bring up. Support FW/SW bring-up and debugging
4. Design different level of C-models

Responsibilities:
1. Major in EE and have Master degree or higher
2. At least 3 years experience in multimedia / video processing and codec domain.
7. Proficient in C/C++
3. Familiar with algorithms of video / image processing and codecs
5. Rich system level knowledge and experience
6. Sound background on the archiect of image / video processing and codec
8. Excellent English communication skills

5. Staff Engineer For Image Processing

Role and Chance:
1. Participate IP and SoC level architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.
2. Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.
3. Go through the FE design flow to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.
4. Write ASIC specific part of test plan. Co-work with verification engineers to prove functional correctness from block level to SoC level
5. Support FW/SW bring-up and debugging
6. Working as the technical point of contact on the ASIC area.
7. Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.

Responsibilities:
1. Major in EE and have Master degree or higher
2. 5 years beyond working experience on ASIC design
3. Must be proficient in Verilog coding, debugging and modeling
4. Must be skilled in ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.
5 Must be skilled in mainstream EDA tools for design and simulation such as ncsim/vcs, RC/DC, PT, Formality/LEC and DFT.
6. Must be familiar with verification methodologies for from block level to SoC level.
7. Should be familiar with shell/perl/tcl programming in linux OS.
8. Should be familiar with P&R and Manufacture tech.
9. Good English hearing, speaking, reading and writing capabilities.
10. Will be a big plus if having strong background on video / image processsing algorithms
11. Will be a big plus if having tape‐out experience.

对上述职位感兴趣的工程师请将简历发送至tobias.gu@amd.com，谢谢。