求助一个verilog语法问题

yanzhengkuaile

assign last_master_ns = rst
                            ? ONE[0+:WIDTH]
                            : upd_last_master
                                ? current_master
                                : last_master_r;
这个0+是什么意思呢？

chlor

没见过，你确定不是sv？

yanzhengkuaile

回复 2# chlor


    我项目V代码里的啊，xilinx官方提供的参考设计

wyj_whu

ONE[0+:WIDTH]
是不是等同于ONE[0:0+WIDTH]
这里的要是不是0+，就还蛮有意义的吧。。。比如，1+，2+之类的、、、
不过我不知道啊。。瞎猜的。。哈哈~
期待高手解答啊、、

chlor

查了一下，verilog-2001支持这种语法，IEEE standard上的：

big_vect[lsb_base_expr +: width_expr]
little_vect[msb_base_expr +: width_expr]
big_vect[msb_base_expr -: width_expr]
little_vect[lsb_base_expr -: width_expr]
The width_expr shall be a constant expression. It also shall not be affected by run-time parameter assignments.
The lsb_base_expr and msb_base_expr can vary at run-time. The first two examples select
bits starting at the base and ascending the bit range. The number of bits selected is equal to the width expression.
The second two examples select bits starting at the base and descending the bit range. Part-selects that
address a range of bits that are completely out of the address bounds of the net, reg, integer, or time,
or when the part-select is x or z, shall yield the value x when read, and shall have no effect on the data
stored when written. Part-selects that are partially out of range shall when read return x for the bits that are
out of range, and when written shall only affect the bits that are in range.

yanzhengkuaile

回复 5# chlor


    非常感谢啊，很细心啊！

quirinus

没用过。。。。。。。。