跪求指导modelsim仿真lpm_rom高阻。

挂在天边的鱼 · 发表于 2011-10-11 22:13:05

回复 1# sara0830

可能是你的rom没生成好，rom没有完成初始化，你能把rom.v的代码贴出来吗？里面应该有一项初始化文件的参数...可以看这个参数是否指定了对应的初始化文件.

sara0830 · 发表于 2011-10-12 10:25:57

回复 11# 挂在天边的鱼

`timescale 1 ns / 1 ns
// synopsys translate_on
module rom (
address,
clock,
q);
input [3:0]  address;
input clock;
output [7:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
  altsyncram_component.clock_enable_input_a = "BYPASS",
  altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
  altsyncram_component.init_file = "rom.rif"
`else
  altsyncram_component.init_file = "rom.hex"
`endif
,
  altsyncram_component.intended_device_family = "Cyclone II",
  altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
  altsyncram_component.lpm_type = "altsyncram",
  altsyncram_component.numwords_a = 16,
  altsyncram_component.operation_mode = "ROM",
  altsyncram_component.outdata_aclr_a = "NONE",
  altsyncram_component.outdata_reg_a = "CLOCK0",
  altsyncram_component.widthad_a = 4,
  altsyncram_component.width_a = 8,
  altsyncram_component.width_byteena_a = 1;

endmodule