|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
ESD Protection Consideration in Nanoscale CMOS Technology
Ming-Dou Ker and Chun-Yu Lin
Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan
Abstract — The thinner gate oxide in nanoscale CMOS
technologies seriously degraded the electrostatic discharge
(ESD) robustness of IC products. As the feature sizes in
nanoscale CMOS technologies are further scaling down, the onchip
ESD protection designs are more challenging. The ESD
protection considerations, including ESD design window, area
efficiency, leakage current, and high-voltage tolerance, were
presented in this abstract. Some possible solutions against these
issues in nanoscale CMOS technologies were also included in
this paper.
Index Terms – CMOS, electrostatic discharge (ESD), onchip
ESD protection. |
|