ESD in Nanoscale CMOS Technology－MD Ker

semico_ljj · 发表于 2011-10-5 20:36:57

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ESD Protection Consideration in Nanoscale CMOS Technology

Ming-Dou Ker and Chun-Yu Lin
Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan

Abstract — The thinner gate oxide in nanoscale CMOS
technologies seriously degraded the electrostatic discharge
(ESD) robustness of IC products. As the feature sizes in
nanoscale CMOS technologies are further scaling down, the onchip
ESD protection designs are more challenging. The ESD
protection considerations, including ESD design window, area
efficiency, leakage current, and high-voltage tolerance, were
presented in this abstract. Some possible solutions against these
issues in nanoscale CMOS technologies were also included in
this paper.

Index Terms – CMOS, electrostatic discharge (ESD), onchip
ESD protection.

semico_ljj · 发表于 2011-10-5 20:38:38

best。。。

floatice · 发表于 2011-10-5 20:42:44

have a look!

mtwumtwu · 发表于 2011-10-6 10:24:28

Good reference for nano-ESD design

tingyc · 发表于 2011-10-6 10:52:42

Good reference for nano-ESD

wallpapers · 发表于 2011-10-7 18:19:44

Jason_ke · 发表于 2011-10-14 12:46:33

好资料，谢谢分享!

volitionccc · 发表于 2011-10-25 11:00:15

nice paper
thanks for sharing

chlliu · 发表于 2011-10-26 21:48:50

很好，谢谢！

xuleiwx · 发表于 2014-4-3 15:04:50

版面很清楚，下载看看

[资料] ESD in Nanoscale CMOS Technology－MD Ker

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