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[资料] ESD in Nanoscale CMOS Technology-MD Ker

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发表于 2011-10-5 20:36:57 | 显示全部楼层 |阅读模式

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ESD Protection Consideration in Nanoscale CMOS Technology

Ming-Dou Ker and Chun-Yu Lin
Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan

Abstract — The thinner gate oxide in nanoscale CMOS
technologies seriously degraded the electrostatic discharge
(ESD) robustness of IC products. As the feature sizes in
nanoscale CMOS technologies are further scaling down, the onchip
ESD protection designs are more challenging. The ESD
protection considerations, including ESD design window, area
efficiency, leakage current, and high-voltage tolerance, were
presented in this abstract. Some possible solutions against these
issues in nanoscale CMOS technologies were also included in
this paper.

Index Terms – CMOS, electrostatic discharge (ESD), onchip
ESD protection.

2011 NANO_ESD protection consideration in nanoscale CMOS technology.pdf

590.45 KB, 下载次数: 79 , 下载积分: 资产 -2 信元, 下载支出 2 信元

 楼主| 发表于 2011-10-5 20:38:38 | 显示全部楼层
best。。。
发表于 2011-10-5 20:42:44 | 显示全部楼层
have a look!
发表于 2011-10-6 10:24:28 | 显示全部楼层
Good reference for nano-ESD design
发表于 2011-10-6 10:52:42 | 显示全部楼层
Good reference for nano-ESD
发表于 2011-10-7 18:19:44 | 显示全部楼层
发表于 2011-10-14 12:46:33 | 显示全部楼层
好资料,谢谢分享!
发表于 2011-10-25 11:00:15 | 显示全部楼层
nice paper
thanks for sharing
发表于 2011-10-26 21:48:50 | 显示全部楼层
很好,谢谢!
发表于 2014-4-3 15:04:50 | 显示全部楼层
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