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本帖最后由 andyjackcao 于 2011-9-19 21:32 编辑
ESD 设计中,相关的rule的check会占据大量的时间。且人工check会引入不确定因素,
导致ESD潜在问题
其实1998年,ESD 大牛已经看到,需要自动化的方法来check这个问题。
Calibre 虽能check ESD的部分rule,但不能检查所有的rule
希望有志之士能构造/共享这样的software.
附件主要内容如下:
In this paper, we report the development of a
unique software program that can detect ESD
design and layout errors. The novel features of
this tool include detection of sensitive spacing
requirements to prevent parasitic current paths,
compatibility of the protection devices to the
circuits being protected, and critical bus resistance
limits for protection efficiency. This tool has been
successfully applied in ASIC designs.
作者:Snehamay Sinha, Hemalata Swaminathan, Gopalarao Kadamati" and Charvaka Duvvury+
Texas Instruments India, MS 4232,Bangalore-560017, India
*ASIC, Texas Instruments Inc., Dallas
+Silicon Technology Development, Texas Instruments Inc., Dallas |
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