请教高手？？？？

wxxxxx · 发表于 2011-9-1 21:34:03

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小妹我最近再学DC的约束脚本，这个语句不知是什么意思，还请各位高手指点
语句如下：set_clock_sense -positive -clocks [get_clocks clk_240k] [get_pins b2v_inst46/U3/Y]

optihack · 发表于 2011-9-1 23:40:36

set the cell U3 to positive_unate within clock_domain clk_240k only,
So that means, cell U3 has nonunateness as its timing sense attribute in the lib.
after set_clock_sense here, a rise of the input to U3 will cause the output of U3(which is Y) to either rise or unchanged.