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Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs.rar
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《Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs》
Jesús Ruiz-Amaya,
Manuel Delgado-Restituto
and
Ángel Rodríguez-Vázquez
chapter 1 Pipeline
ADC Overview
This chapter provides a brief introduction to pipeline converters. Before describing their inner structure and basic operation principles, a designer must know the ideas underlying the analog-to-digital conversion process. For this purpose, Sect. 1.1 provides a brief overview of the fundamentals of analog-to-digital conversion. Subsequently, pipeline converters will be introduced in Sect. 1.2, emphasizing their main characteristics and describing their basic building blocks. As conclusion to the chapter, an overview of the current trends for the enhancement of pipeline converters will be provided.
chapter2 Design Methodologies for Pipeline ADCs
As explained in Chap. 1, the design of ADCs in adverse digital technologies is a major challenge for designers. This challenge becomes more significant with the scaling of technology which brings about new obstacles (leakage currents, increment of the relative variability of technological parameters, low power supplies, etc). In order to overcome this challenge, designers need to develop robust design methodologies or have access to CAD tools which will allow them to simplify the design procedure. This chapter deals with this issue. Firstly, a brief overview of a conventional top-down design methodology will be given, describing the different hierarchical levels into which the design procedure is split. This will be followed by an explanation of the tools required and needs for supporting the top-down design methodology. Finally, we will present our proposed design methodology, emphasizing the improvements with respect to the conventional ones.
Chapter 3 Pipeline ADC Electrical-Level Synthesis Tool
As explained in the previous chapter, the design methodology proposed consists of three key components: a behavioural simulator to evaluate the performance of the ADC, a set of Matlab routines to map the high-level specifications onto transistor-level specifications, and an optimization algorithm to find the most suitable solution in terms of power consumption and silicon area
Chapter4 Behavioural Modelling of Pipeline ADCs
The basic building blocks of a pipeline architecture are subjected to several non-idealities which degrade the converter performance considerably. Thus, the development of models which take into account all these non-idealities is essential for the correct evaluation of the performance of the pipeline ADC. These models must satisfy two fundamental requirements: reliability and efficiency. The former will determine the verisimilitude between the actual performance of the ADC and the prediction of the models, while the latter will determine the time required for the evaluation of this performance. It is obvious that accurate and speedy models are desirable. However, there is a strong trade-off between both requirements, that is to say, the more accurate the models, the more complex they will be, and therefore, the greater the CPU time required to evaluate the converter performance. To overcome this trade-off, the so-called behavioural modelling technique has been successfully used in recent years [101, 107, 116, 117]. This technique provides reasonable precision, as well as low CPU requirements. Hence, we have opted for developing models for the basic building blocks of the pipeline converter using this technique.
chapter5 Case Study: Design of a 10bit@60MS Pipeline ADC
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chapter6 Experimental Results and State of the Art
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chapter7 Conclusions and Future Lines of Research
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发表于 2011-8-7 20:50:46
