SystemVerilog includes a number of enhancements to the Verilog language that are useful for FPGA design. Synthesis tools from FPGA vendors and EDA tool vendors enable SystemVerilog designs to be described using easier-to-understand styles and higher levels of abstraction than were possible in Verilog, speeding up the coding process and easing reuse. This article looks at how synthesisable SystemVerilog can be written for various functional blocks commonly used in FPGAs. An example design based around a generic bus with multiple arbitrated masters and multiple slaves is used to illustrate synthesisable coding styles. Some of the techniques described here have been borrowed from VHDL while others are only possible with SystemVerilog.
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发表于 2011-6-18 22:00:10
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