大版主还有一个timing violation问题想请问你!!

yifan225

对于设计中的异步信号，因为它的变化沿有可能与时钟同时变化，这时会出现一些timing violation的信息，请问这对设计有影响么？是不是要修正呢?
DFT后仿真显示的违背信息:
Warning!  Timing violation
$setuphold<setup>( posedge CK &&& RN&~TE:688505675 NS, negedge D:688505674890 PS,  0.27 : 270 PS,  -0.06 : -60 PS );  File: ./smic25.v, line = 7583       Scope:system_check_stimulus_design.top_process.top_selftest1.testout1.Txd_Ack_r1_reg
Time: 688505675 NS

老扁

这个不用管。
你可以用set_false_path来去掉这种时序检查。
但在接口设计上你要严格按异步接口的方法来做，否则会采样错误。

yifan225

你说的是在DC里面用set_false_path指令是么？
DC里面都是这样用的呀！！

yifan225

DC出来和DFT出来的都没有时序违背的呀!!
大版主,请给我确认一下

francisus

If you have an asynchronous path, say signal X is sent from clock domain A,
first sampled to Y in clock domain B, then sampled again to Z in clock domain B,
from X to Y is asynchronous,
In DC and STA, you need to set_false_path -from X -to Y, then any timing violation
from X to Y would not be reported;
In simulation with timing, the simulator does not know X to Y is a false
path, so it reports errors. It is fine because you know it is an
asynchronous path and Y is not used anywhere else but at Z.

conghung2012

还是没搞清。