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PLL noise analysis with HSPICE-RF : 3rd Edition
A critical aspect of PLL design is meeting phase noise and jitter specifications. Accurate
predictions of PLL noise are possible through circuit simulation, but the steps required to do so
are often shrouded in mystery or considered too challenging to undertake. Phase locked loops
are characterized with numerous time and frequency domain measurements, usually spanning
several time scales and frequency ranges. The challenge with simulation is correctly constructing
test benches that can efficiently extract key performance metrics without the simulations requiring
days or even weeks of run-time to complete. This white paper describes a procedure for
efficiently extracting key noise measurements for a phase locked loop using HSPICE RF. The
procedure takes advantage of several unique capabilities of HSPICE RF for accurately predicting
oscillator steady-state and phase noise characteristics. |
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